23.26%  ↗↗↗↗  0x0000ffff702e4130:   add	w20, w20, #0x1              ;*iinc {reexecute=0 rethrow=0 return_oop=0}
   1.57%  ││││  0x0000ffff702e4134:   cmp	w20, w19
          ││││  0x0000ffff702e4138:   b.ge	0x0000ffff702e408c  // b.tcont;*aload_1 {reexecute=0 rethrow=0 return_oop=0}
   1.94%  ││││  0x0000ffff702e413c:   add	x10, x17, w20, sxtw #3
   1.10%  ││││  0x0000ffff702e4140:   ldr	x22, [x10, #16]             ;*aaload {reexecute=0 rethrow=0 return_oop=0}
   1.88%  ││││  0x0000ffff702e4144:   ldp	x11, x10, [x21, #16]        ;*getfield arg$2 {reexecute=0 rethrow=0 return_oop=0}
   1.14%  ││││  0x0000ffff702e4148:   ldr	x23, [x21, #32]             ;*getfield arg$3 {reexecute=0 rethrow=0 return_oop=0}
   1.07%  ││││  0x0000ffff702e414c:   ldr	w0, [x22, #8]               ; implicit exception: dispatches to 0x0000ffff702e4ae8
   0.09%  ││││  0x0000ffff702e4150:   mov	x2, #0x1100000             	// #17825792
   2.64%  ││││  0x0000ffff702e4154:   movk	x2, #0x7c88
   1.00%  ││││  0x0000ffff702e4158:   cmp	w0, w2
          ││││  0x0000ffff702e415c:   b.ne	0x0000ffff702e4974  // b.any;*checkcast {reexecute=0 rethrow=0 return_oop=0}
   1.45%  ││││  0x0000ffff702e4160:   ldr	d16, [x11, #16]             ; implicit exception: dispatches to 0x0000ffff702e4b18
   1.94%  ││││  0x0000ffff702e4164:   ldr	d17, [x22, #16]
   1.14%  ││││  0x0000ffff702e4168:   ldr	d18, [x11, #24]
   1.28%  ││││  0x0000ffff702e416c:   ldr	d19, [x22, #24]
   1.10%  ││││  0x0000ffff702e4170:   ldr	d20, [x11, #32]
   1.16%  ││││  0x0000ffff702e4174:   ldr	d21, [x22, #32]
   1.23%  ││││  0x0000ffff702e4178:   ldr	d22, [x10, #16]             ; implicit exception: dispatches to 0x0000ffff702e4b30
   1.18%  ││││  0x0000ffff702e417c:   fsub	d16, d17, d16               ;*dsub {reexecute=0 rethrow=0 return_oop=0}
   1.05%  ││││  0x0000ffff702e4180:   fsub	d17, d19, d18               ;*dsub {reexecute=0 rethrow=0 return_oop=0}
   0.36%  ││││  0x0000ffff702e4184:   fmul	d16, d16, d16
   0.68%  ││││  0x0000ffff702e4188:   fmul	d17, d17, d17
   0.37%  ││││  0x0000ffff702e418c:   fsub	d18, d21, d20               ;*dsub {reexecute=0 rethrow=0 return_oop=0}
   0.74%  ││││  0x0000ffff702e4190:   fadd	d16, d16, d17
   0.71%  ││││  0x0000ffff702e4194:   fmul	d17, d18, d18
   0.35%  ││││  0x0000ffff702e4198:   fadd	d16, d16, d17               ;*dadd {reexecute=0 rethrow=0 return_oop=0}
   0.70%  ││││  0x0000ffff702e419c:   fcmp	d22, d16
   1.03%  ╰│││  0x0000ffff702e41a0:   b.le	0x0000ffff702e4130          ;*ifge {reexecute=0 rethrow=0 return_oop=0}
   1.98%   │││  0x0000ffff702e41a4:   str	d16, [x10, #16]             ;*putfield elem {reexecute=0 rethrow=0 return_oop=0}
   3.17%   │││  0x0000ffff702e41a8:   cbz	x23, 0x0000ffff702e473c
   0.14%   │││  0x0000ffff702e41ac:   ldrsb	w11, [x28, #56]
   1.12%   │││  0x0000ffff702e41b0:   cbnz	w11, 0x0000ffff702e4218
   0.42%   │││  0x0000ffff702e41b4:   mov	x10, x23
   0.09%   │││  0x0000ffff702e41b8:   mov	x11, x22
   0.06%   │││  0x0000ffff702e41bc:   eor	x11, x11, x10
   0.10%   │││  0x0000ffff702e41c0:   lsr	x11, x11, #21
   0.09%   │││  0x0000ffff702e41c4:   str	x22, [x23, #16]
   0.09%   ╰││  0x0000ffff702e41c8:   cbz	x11, 0x0000ffff702e4130
   0.09%    ││  0x0000ffff702e41cc:   lsr	x10, x10, #9
   0.01%    ││  0x0000ffff702e41d0:   mov	x11, #0xc000                	// #49152
   0.06%    ││  0x0000ffff702e41d4:   movk	x11, #0x664c, lsl #16
   0.01%    ││  0x0000ffff702e41d8:   movk	x11, #0xff7e, lsl #32
   0.06%    ││  0x0000ffff702e41dc:   add	x0, x11, x10
   0.09%    ││  0x0000ffff702e41e0:   ldrsb	w10, [x0]
   0.98%    ││  0x0000ffff702e41e4:   cmp	w10, #0x2
            ╰│  0x0000ffff702e41e8:   b.eq	0x0000ffff702e4130  // b.none