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## src/cpu/x86/vm/assembler_x86.cpp

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    *** 2327,2336 ****
    --- 2327,2343 ----
      void Assembler::orl(Register dst, Register src) {
        (void) prefix_and_encode(dst->encoding(), src->encoding());
        emit_arith(0x0B, 0xC0, dst, src);
      }

    + void Assembler::orl(Address dst, Register src) {
    +   InstructionMark im(this);
    +   prefix(dst, src);
    +   emit_int8(0x09);
    +   emit_operand(src, dst);
    + }
    +
      void Assembler::packuswb(XMMRegister dst, Address src) {
        NOT_LP64(assert(VM_Version::supports_sse2(), ""));
        assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
        emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
      }
    *** 5622,5631 ****
    --- 5629,5651 ----
          emit_int8((unsigned char)(0xD0 | encode));
          emit_int8(imm8);
        }
      }

    + void Assembler::rcrq(Register dst, int imm8) {
    +   assert(isShiftCount(imm8 >> 1), "illegal shift count");
    +   int encode = prefixq_and_encode(dst->encoding());
    +   if (imm8 == 1) {
    +     emit_int8((unsigned char)0xD1);
    +     emit_int8((unsigned char)(0xD8 | encode));
    +   } else {
    +     emit_int8((unsigned char)0xC1);
    +     emit_int8((unsigned char)(0xD8 | encode));
    +     emit_int8(imm8);
    +   }
    + }
    +
      void Assembler::rorq(Register dst, int imm8) {
        assert(isShiftCount(imm8 >> 1), "illegal shift count");
        int encode = prefixq_and_encode(dst->encoding());
        if (imm8 == 1) {
          emit_int8((unsigned char)0xD1);

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