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## src/cpu/x86/vm/assembler_x86.cpp

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    2312   emit_arith_operand(0x81, rcx, dst, imm32);
    2313 }
    2314
    2315 void Assembler::orl(Register dst, int32_t imm32) {
    2316   prefix(dst);
    2317   emit_arith(0x81, 0xC8, dst, imm32);
    2318 }
    2319
    2320 void Assembler::orl(Register dst, Address src) {
    2321   InstructionMark im(this);
    2322   prefix(src, dst);
    2323   emit_int8(0x0B);
    2324   emit_operand(dst, src);
    2325 }
    2326
    2327 void Assembler::orl(Register dst, Register src) {
    2328   (void) prefix_and_encode(dst->encoding(), src->encoding());
    2329   emit_arith(0x0B, 0xC0, dst, src);
    2330 }
    2331

    2332 void Assembler::packuswb(XMMRegister dst, Address src) {
    2333   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
    2334   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
    2335   emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
    2336 }
    2337
    2338 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
    2339   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
    2340   emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
    2341 }
    2342
    2343 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
    2344   assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
    2345   emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector256);
    2346 }
    2347
    2348 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256) {
    2349   assert(VM_Version::supports_avx2(), "");
    2350   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector256);
    2351   emit_int8(0x00);
    5603   movq(Address(rsp, wordSize), r14);
    5604   movq(Address(rsp, 0), r15);
    5605 }
    5606
    5607 void Assembler::pushq(Address src) {
    5608   InstructionMark im(this);
    5609   prefixq(src);
    5610   emit_int8((unsigned char)0xFF);
    5611   emit_operand(rsi, src);
    5612 }
    5613
    5614 void Assembler::rclq(Register dst, int imm8) {
    5615   assert(isShiftCount(imm8 >> 1), "illegal shift count");
    5616   int encode = prefixq_and_encode(dst->encoding());
    5617   if (imm8 == 1) {
    5618     emit_int8((unsigned char)0xD1);
    5619     emit_int8((unsigned char)(0xD0 | encode));
    5620   } else {
    5621     emit_int8((unsigned char)0xC1);
    5622     emit_int8((unsigned char)(0xD0 | encode));

    5623     emit_int8(imm8);
    5624   }
    5625 }
    5626
    5627 void Assembler::rorq(Register dst, int imm8) {
    5628   assert(isShiftCount(imm8 >> 1), "illegal shift count");
    5629   int encode = prefixq_and_encode(dst->encoding());
    5630   if (imm8 == 1) {
    5631     emit_int8((unsigned char)0xD1);
    5632     emit_int8((unsigned char)(0xC8 | encode));
    5633   } else {
    5634     emit_int8((unsigned char)0xC1);
    5635     emit_int8((unsigned char)(0xc8 | encode));
    5636     emit_int8(imm8);
    5637   }
    5638 }
    5639
    5640 void Assembler::rorxq(Register dst, Register src, int imm8) {
    5641   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
    5642   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, true, false);
    2312   emit_arith_operand(0x81, rcx, dst, imm32);
    2313 }
    2314
    2315 void Assembler::orl(Register dst, int32_t imm32) {
    2316   prefix(dst);
    2317   emit_arith(0x81, 0xC8, dst, imm32);
    2318 }
    2319
    2320 void Assembler::orl(Register dst, Address src) {
    2321   InstructionMark im(this);
    2322   prefix(src, dst);
    2323   emit_int8(0x0B);
    2324   emit_operand(dst, src);
    2325 }
    2326
    2327 void Assembler::orl(Register dst, Register src) {
    2328   (void) prefix_and_encode(dst->encoding(), src->encoding());
    2329   emit_arith(0x0B, 0xC0, dst, src);
    2330 }
    2331
    2332 void Assembler::orl(Address dst, Register src) {
    2333   InstructionMark im(this);
    2334   prefix(dst, src);
    2335   emit_int8(0x09);
    2336   emit_operand(src, dst);
    2337 }
    2338
    2339 void Assembler::packuswb(XMMRegister dst, Address src) {
    2340   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
    2341   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
    2342   emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
    2343 }
    2344
    2345 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
    2346   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
    2347   emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
    2348 }
    2349
    2350 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
    2351   assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
    2352   emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector256);
    2353 }
    2354
    2355 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256) {
    2356   assert(VM_Version::supports_avx2(), "");
    2357   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector256);
    2358   emit_int8(0x00);
    5610   movq(Address(rsp, wordSize), r14);
    5611   movq(Address(rsp, 0), r15);
    5612 }
    5613
    5614 void Assembler::pushq(Address src) {
    5615   InstructionMark im(this);
    5616   prefixq(src);
    5617   emit_int8((unsigned char)0xFF);
    5618   emit_operand(rsi, src);
    5619 }
    5620
    5621 void Assembler::rclq(Register dst, int imm8) {
    5622   assert(isShiftCount(imm8 >> 1), "illegal shift count");
    5623   int encode = prefixq_and_encode(dst->encoding());
    5624   if (imm8 == 1) {
    5625     emit_int8((unsigned char)0xD1);
    5626     emit_int8((unsigned char)(0xD0 | encode));
    5627   } else {
    5628     emit_int8((unsigned char)0xC1);
    5629     emit_int8((unsigned char)(0xD0 | encode));
    5630     emit_int8(imm8);
    5631   }
    5632 }
    5633
    5634 void Assembler::rcrq(Register dst, int imm8) {
    5635   assert(isShiftCount(imm8 >> 1), "illegal shift count");
    5636   int encode = prefixq_and_encode(dst->encoding());
    5637   if (imm8 == 1) {
    5638     emit_int8((unsigned char)0xD1);
    5639     emit_int8((unsigned char)(0xD8 | encode));
    5640   } else {
    5641     emit_int8((unsigned char)0xC1);
    5642     emit_int8((unsigned char)(0xD8 | encode));
    5643     emit_int8(imm8);
    5644   }
    5645 }
    5646
    5647 void Assembler::rorq(Register dst, int imm8) {
    5648   assert(isShiftCount(imm8 >> 1), "illegal shift count");
    5649   int encode = prefixq_and_encode(dst->encoding());
    5650   if (imm8 == 1) {
    5651     emit_int8((unsigned char)0xD1);
    5652     emit_int8((unsigned char)(0xC8 | encode));
    5653   } else {
    5654     emit_int8((unsigned char)0xC1);
    5655     emit_int8((unsigned char)(0xc8 | encode));
    5656     emit_int8(imm8);
    5657   }
    5658 }
    5659
    5660 void Assembler::rorxq(Register dst, Register src, int imm8) {
    5661   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
    5662   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, true, false);

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