       1 /*
       2  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
       3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
       4  *
       5  * This code is free software; you can redistribute it and/or modify it
       6  * under the terms of the GNU General Public License version 2 only, as
       7  * published by the Free Software Foundation.
       8  *
       9  * This code is distributed in the hope that it will be useful, but WITHOUT
      10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
      11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
      12  * version 2 for more details (a copy is included in the LICENSE file that
      13  * accompanied this code).
      14  *
      15  * You should have received a copy of the GNU General Public License version
      16  * 2 along with this work; if not, write to the Free Software Foundation,
      17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
      18  *
      19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
      20  * or visit www.oracle.com if you need additional information or have any
      21  * questions.
      22  *
      23  */
      24
      25 #include "precompiled.hpp"
      26 #include "asm/macroAssembler.hpp"
      27 #include "asm/macroAssembler.inline.hpp"
      28 #include "memory/resourceArea.hpp"
      29 #include "runtime/java.hpp"
      30 #include "runtime/os.hpp"
      31 #include "runtime/stubCodeGenerator.hpp"
      32 #include "vm_version_x86.hpp"
      33
      34
      35 int VM_Version::_cpu;
      36 int VM_Version::_model;
      37 int VM_Version::_stepping;
      38 int VM_Version::_cpuFeatures;
      39 const char*           VM_Version::_features_str = "";
      40 VM_Version::CpuidInfo VM_Version::_cpuid_info   = { 0, };
      41
      42 // Address of instruction which causes SEGV
      43 address VM_Version::_cpuinfo_segv_addr = 0;
      44 // Address of instruction after the one which causes SEGV
      45 address VM_Version::_cpuinfo_cont_addr = 0;
      46
      47 static BufferBlob* stub_blob;
      48 static const int stub_size = 600;
      49
      50 extern "C" {
      51   typedef void (*get_cpu_info_stub_t)(void*);
      52 }
      53 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
      54
      55
      56 class VM_Version_StubGenerator: public StubCodeGenerator {
      57  public:
      58
      59   VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
      60
      61   address generate_get_cpu_info() {
      62     // Flags to test CPU type.
      63     const uint32_t HS_EFL_AC           = 0x40000;
      64     const uint32_t HS_EFL_ID           = 0x200000;
      65     // Values for when we don't have a CPUID instruction.
      66     const int      CPU_FAMILY_SHIFT = 8;
      67     const uint32_t CPU_FAMILY_386   = (3 << CPU_FAMILY_SHIFT);
      68     const uint32_t CPU_FAMILY_486   = (4 << CPU_FAMILY_SHIFT);
      69
      70     Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
      71     Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done;
      72
      73     StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
      74 #   define __ _masm->
      75
      76     address start = __ pc();
      77
      78     //
      79     // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
      80     //
      81     // LP64: rcx and rdx are first and second argument registers on windows
      82
      83     __ push(rbp);
      84 #ifdef _LP64
      85     __ mov(rbp, c_rarg0); // cpuid_info address
      86 #else
      87     __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
      88 #endif
      89     __ push(rbx);
      90     __ push(rsi);
      91     __ pushf();          // preserve rbx, and flags
      92     __ pop(rax);
      93     __ push(rax);
      94     __ mov(rcx, rax);
      95     //
      96     // if we are unable to change the AC flag, we have a 386
      97     //
      98     __ xorl(rax, HS_EFL_AC);
      99     __ push(rax);
     100     __ popf();
     101     __ pushf();
     102     __ pop(rax);
     103     __ cmpptr(rax, rcx);
     104     __ jccb(Assembler::notEqual, detect_486);
     105
     106     __ movl(rax, CPU_FAMILY_386);
     107     __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
     108     __ jmp(done);
     109
     110     //
     111     // If we are unable to change the ID flag, we have a 486 which does
     112     // not support the "cpuid" instruction.
     113     //
     114     __ bind(detect_486);
     115     __ mov(rax, rcx);
     116     __ xorl(rax, HS_EFL_ID);
     117     __ push(rax);
     118     __ popf();
     119     __ pushf();
     120     __ pop(rax);
     121     __ cmpptr(rcx, rax);
     122     __ jccb(Assembler::notEqual, detect_586);
     123
     124     __ bind(cpu486);
     125     __ movl(rax, CPU_FAMILY_486);
     126     __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
     127     __ jmp(done);
     128
     129     //
     130     // At this point, we have a chip which supports the "cpuid" instruction
     131     //
     132     __ bind(detect_586);
     133     __ xorl(rax, rax);
     134     __ cpuid();
     135     __ orl(rax, rax);
     136     __ jcc(Assembler::equal, cpu486);   // if cpuid doesn't support an input
     137                                         // value of at least 1, we give up and
     138                                         // assume a 486
     139     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
     140     __ movl(Address(rsi, 0), rax);
     141     __ movl(Address(rsi, 4), rbx);
     142     __ movl(Address(rsi, 8), rcx);
     143     __ movl(Address(rsi,12), rdx);
     144
     145     __ cmpl(rax, 0xa);                  // Is cpuid(0xB) supported?
     146     __ jccb(Assembler::belowEqual, std_cpuid4);
     147
     148     //
     149     // cpuid(0xB) Processor Topology
     150     //
     151     __ movl(rax, 0xb);
     152     __ xorl(rcx, rcx);   // Threads level
     153     __ cpuid();
     154
     155     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
     156     __ movl(Address(rsi, 0), rax);
     157     __ movl(Address(rsi, 4), rbx);
     158     __ movl(Address(rsi, 8), rcx);
     159     __ movl(Address(rsi,12), rdx);
     160
     161     __ movl(rax, 0xb);
     162     __ movl(rcx, 1);     // Cores level
     163     __ cpuid();
     164     __ push(rax);
     165     __ andl(rax, 0x1f);  // Determine if valid topology level
     166     __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
     167     __ andl(rax, 0xffff);
     168     __ pop(rax);
     169     __ jccb(Assembler::equal, std_cpuid4);
     170
     171     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
     172     __ movl(Address(rsi, 0), rax);
     173     __ movl(Address(rsi, 4), rbx);
     174     __ movl(Address(rsi, 8), rcx);
     175     __ movl(Address(rsi,12), rdx);
     176
     177     __ movl(rax, 0xb);
     178     __ movl(rcx, 2);     // Packages level
     179     __ cpuid();
     180     __ push(rax);
     181     __ andl(rax, 0x1f);  // Determine if valid topology level
     182     __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
     183     __ andl(rax, 0xffff);
     184     __ pop(rax);
     185     __ jccb(Assembler::equal, std_cpuid4);
     186
     187     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
     188     __ movl(Address(rsi, 0), rax);
     189     __ movl(Address(rsi, 4), rbx);
     190     __ movl(Address(rsi, 8), rcx);
     191     __ movl(Address(rsi,12), rdx);
     192
     193     //
     194     // cpuid(0x4) Deterministic cache params
     195     //
     196     __ bind(std_cpuid4);
     197     __ movl(rax, 4);
     198     __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
     199     __ jccb(Assembler::greater, std_cpuid1);
     200
     201     __ xorl(rcx, rcx);   // L1 cache
     202     __ cpuid();
     203     __ push(rax);
     204     __ andl(rax, 0x1f);  // Determine if valid cache parameters used
     205     __ orl(rax, rax);    // eax[4:0] == 0 indicates invalid cache
     206     __ pop(rax);
     207     __ jccb(Assembler::equal, std_cpuid1);
     208
     209     __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
     210     __ movl(Address(rsi, 0), rax);
     211     __ movl(Address(rsi, 4), rbx);
     212     __ movl(Address(rsi, 8), rcx);
     213     __ movl(Address(rsi,12), rdx);
     214
     215     //
     216     // Standard cpuid(0x1)
     217     //
     218     __ bind(std_cpuid1);
     219     __ movl(rax, 1);
     220     __ cpuid();
     221     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
     222     __ movl(Address(rsi, 0), rax);
     223     __ movl(Address(rsi, 4), rbx);
     224     __ movl(Address(rsi, 8), rcx);
     225     __ movl(Address(rsi,12), rdx);
     226
     227     //
     228     // Check if OS has enabled XGETBV instruction to access XCR0
     229     // (OSXSAVE feature flag) and CPU supports AVX
     230     //
     231     __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
     232     __ cmpl(rcx, 0x18000000);
     233     __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
     234
     235     //
     236     // XCR0, XFEATURE_ENABLED_MASK register
     237     //
     238     __ xorl(rcx, rcx);   // zero for XCR0 register
     239     __ xgetbv();
     240     __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
     241     __ movl(Address(rsi, 0), rax);
     242     __ movl(Address(rsi, 4), rdx);
     243
     244     __ andl(rax, 0x6); // xcr0 bits sse | ymm
     245     __ cmpl(rax, 0x6);
     246     __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
     247
     248     //
     249     // Some OSs have a bug when upper 128bits of YMM
     250     // registers are not restored after a signal processing.
     251     // Generate SEGV here (reference through NULL)
     252     // and check upper YMM bits after it.
     253     //
     254     VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
     255     intx saved_useavx = UseAVX;
     256     intx saved_usesse = UseSSE;
     257     UseAVX = 1;
     258     UseSSE = 2;
     259
     260     // load value into all 32 bytes of ymm7 register
     261     __ movl(rcx, VM_Version::ymm_test_value());
     262
     263     __ movdl(xmm0, rcx);
     264     __ pshufd(xmm0, xmm0, 0x00);
     265     __ vinsertf128h(xmm0, xmm0, xmm0);
     266     __ vmovdqu(xmm7, xmm0);
     267 #ifdef _LP64
     268     __ vmovdqu(xmm8,  xmm0);
     269     __ vmovdqu(xmm15, xmm0);
     270 #endif
     271
     272     __ xorl(rsi, rsi);
     273     VM_Version::set_cpuinfo_segv_addr( __ pc() );
     274     // Generate SEGV
     275     __ movl(rax, Address(rsi, 0));
     276
     277     VM_Version::set_cpuinfo_cont_addr( __ pc() );
     278     // Returns here after signal. Save xmm0 to check it later.
     279     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
     280     __ vmovdqu(Address(rsi,  0), xmm0);
     281     __ vmovdqu(Address(rsi, 32), xmm7);
     282 #ifdef _LP64
     283     __ vmovdqu(Address(rsi, 64), xmm8);
     284     __ vmovdqu(Address(rsi, 96), xmm15);
     285 #endif
     286
     287     VM_Version::clean_cpuFeatures();
     288     UseAVX = saved_useavx;
     289     UseSSE = saved_usesse;
     290
     291     //
     292     // cpuid(0x7) Structured Extended Features
     293     //
     294     __ bind(sef_cpuid);
     295     __ movl(rax, 7);
     296     __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
     297     __ jccb(Assembler::greater, ext_cpuid);
     298
     299     __ xorl(rcx, rcx);
     300     __ cpuid();
     301     __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
     302     __ movl(Address(rsi, 0), rax);
     303     __ movl(Address(rsi, 4), rbx);
     304
     305     //
     306     // Extended cpuid(0x80000000)
     307     //
     308     __ bind(ext_cpuid);
     309     __ movl(rax, 0x80000000);
     310     __ cpuid();
     311     __ cmpl(rax, 0x80000000);     // Is cpuid(0x80000001) supported?
     312     __ jcc(Assembler::belowEqual, done);
     313     __ cmpl(rax, 0x80000004);     // Is cpuid(0x80000005) supported?
     314     __ jccb(Assembler::belowEqual, ext_cpuid1);
     315     __ cmpl(rax, 0x80000006);     // Is cpuid(0x80000007) supported?
     316     __ jccb(Assembler::belowEqual, ext_cpuid5);
     317     __ cmpl(rax, 0x80000007);     // Is cpuid(0x80000008) supported?
     318     __ jccb(Assembler::belowEqual, ext_cpuid7);
     319     //
     320     // Extended cpuid(0x80000008)
     321     //
     322     __ movl(rax, 0x80000008);
     323     __ cpuid();
     324     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
     325     __ movl(Address(rsi, 0), rax);
     326     __ movl(Address(rsi, 4), rbx);
     327     __ movl(Address(rsi, 8), rcx);
     328     __ movl(Address(rsi,12), rdx);
     329
     330     //
     331     // Extended cpuid(0x80000007)
     332     //
     333     __ bind(ext_cpuid7);
     334     __ movl(rax, 0x80000007);
     335     __ cpuid();
     336     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
     337     __ movl(Address(rsi, 0), rax);
     338     __ movl(Address(rsi, 4), rbx);
     339     __ movl(Address(rsi, 8), rcx);
     340     __ movl(Address(rsi,12), rdx);
     341
     342     //
     343     // Extended cpuid(0x80000005)
     344     //
     345     __ bind(ext_cpuid5);
     346     __ movl(rax, 0x80000005);
     347     __ cpuid();
     348     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
     349     __ movl(Address(rsi, 0), rax);
     350     __ movl(Address(rsi, 4), rbx);
     351     __ movl(Address(rsi, 8), rcx);
     352     __ movl(Address(rsi,12), rdx);
     353
     354     //
     355     // Extended cpuid(0x80000001)
     356     //
     357     __ bind(ext_cpuid1);
     358     __ movl(rax, 0x80000001);
     359     __ cpuid();
     360     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
     361     __ movl(Address(rsi, 0), rax);
     362     __ movl(Address(rsi, 4), rbx);
     363     __ movl(Address(rsi, 8), rcx);
     364     __ movl(Address(rsi,12), rdx);
     365
     366     //
     367     // return
     368     //
     369     __ bind(done);
     370     __ popf();
     371     __ pop(rsi);
     372     __ pop(rbx);
     373     __ pop(rbp);
     374     __ ret(0);
     375
     376 #   undef __
     377
     378     return start;
     379   };
     380 };
     381
     382
     383 void VM_Version::get_cpu_info_wrapper() {
     384   get_cpu_info_stub(&_cpuid_info);
     385 }
     386
     387 #ifndef CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED
     388   #define CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(f) f()
     389 #endif
     390
     391 void VM_Version::get_processor_features() {
     392
     393   _cpu = 4; // 486 by default
     394   _model = 0;
     395   _stepping = 0;
     396   _cpuFeatures = 0;
     397   _logical_processors_per_package = 1;
     398   // i486 internal cache is both I&D and has a 16-byte line size
     399   _L1_data_cache_line_size = 16;
     400
     401   if (!Use486InstrsOnly) {
     402     // Get raw processor info
     403
     404     // Some platforms (like Win*) need a wrapper around here
     405     // in order to properly handle SEGV for YMM registers test.
     406     CALL_TEST_FUNC_WITH_WRAPPER_IF_NEEDED(get_cpu_info_wrapper);
     407
     408     assert_is_initialized();
     409     _cpu = extended_cpu_family();
     410     _model = extended_cpu_model();
     411     _stepping = cpu_stepping();
     412
     413     if (cpu_family() > 4) { // it supports CPUID
     414       _cpuFeatures = feature_flags();
     415       // Logical processors are only available on P4s and above,
     416       // and only if hyperthreading is available.
     417       _logical_processors_per_package = logical_processor_count();
     418       _L1_data_cache_line_size = L1_line_size();
     419     }
     420   }
     421
     422   _supports_cx8 = supports_cmpxchg8();
     423   // xchg and xadd instructions
     424   _supports_atomic_getset4 = true;
     425   _supports_atomic_getadd4 = true;
     426   LP64_ONLY(_supports_atomic_getset8 = true);
     427   LP64_ONLY(_supports_atomic_getadd8 = true);
     428
     429 #ifdef _LP64
     430   // OS should support SSE for x64 and hardware should support at least SSE2.
     431   if (!VM_Version::supports_sse2()) {
     432     vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
     433   }
     434   // in 64 bit the use of SSE2 is the minimum
     435   if (UseSSE < 2) UseSSE = 2;
     436 #endif
     437
     438 #ifdef AMD64
     439   // flush_icache_stub have to be generated first.
     440   // That is why Icache line size is hard coded in ICache class,
     441   // see icache_x86.hpp. It is also the reason why we can't use
     442   // clflush instruction in 32-bit VM since it could be running
     443   // on CPU which does not support it.
     444   //
     445   // The only thing we can do is to verify that flushed
     446   // ICache::line_size has correct value.
     447   guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
     448   // clflush_size is size in quadwords (8 bytes).
     449   guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
     450 #endif
     451
     452   // If the OS doesn't support SSE, we can't use this feature even if the HW does
     453   if (!os::supports_sse())
     454     _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
     455
     456   if (UseSSE < 4) {
     457     _cpuFeatures &= ~CPU_SSE4_1;
     458     _cpuFeatures &= ~CPU_SSE4_2;
     459   }
     460
     461   if (UseSSE < 3) {
     462     _cpuFeatures &= ~CPU_SSE3;
     463     _cpuFeatures &= ~CPU_SSSE3;
     464     _cpuFeatures &= ~CPU_SSE4A;
     465   }
     466
     467   if (UseSSE < 2)
     468     _cpuFeatures &= ~CPU_SSE2;
     469
     470   if (UseSSE < 1)
     471     _cpuFeatures &= ~CPU_SSE;
     472
     473   if (UseAVX < 2)
     474     _cpuFeatures &= ~CPU_AVX2;
     475
     476   if (UseAVX < 1)
     477     _cpuFeatures &= ~CPU_AVX;
     478
     479   if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
     480     _cpuFeatures &= ~CPU_AES;
     481
     482   if (logical_processors_per_package() == 1) {
     483     // HT processor could be installed on a system which doesn't support HT.
     484     _cpuFeatures &= ~CPU_HT;
     485   }
     486
     487   char buf[256];
     488   jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
     489                cores_per_cpu(), threads_per_core(),
     490                cpu_family(), _model, _stepping,
     491                (supports_cmov() ? ", cmov" : ""),
     492                (supports_cmpxchg8() ? ", cx8" : ""),
     493                (supports_fxsr() ? ", fxsr" : ""),
     494                (supports_mmx()  ? ", mmx"  : ""),
     495                (supports_sse()  ? ", sse"  : ""),
     496                (supports_sse2() ? ", sse2" : ""),
     497                (supports_sse3() ? ", sse3" : ""),
     498                (supports_ssse3()? ", ssse3": ""),
     499                (supports_sse4_1() ? ", sse4.1" : ""),
     500                (supports_sse4_2() ? ", sse4.2" : ""),
     501                (supports_popcnt() ? ", popcnt" : ""),
     502                (supports_avx()    ? ", avx" : ""),
     503                (supports_avx2()   ? ", avx2" : ""),
     504                (supports_aes()    ? ", aes" : ""),
     505                (supports_clmul()  ? ", clmul" : ""),
     506                (supports_erms()   ? ", erms" : ""),
     507                (supports_rtm()    ? ", rtm" : ""),
     508                (supports_mmx_ext() ? ", mmxext" : ""),
     509                (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
     510                (supports_lzcnt()   ? ", lzcnt": ""),
     511                (supports_sse4a()   ? ", sse4a": ""),
     512                (supports_ht() ? ", ht": ""),
     513                (supports_tsc() ? ", tsc": ""),
     514                (supports_tscinv_bit() ? ", tscinvbit": ""),
     515                (supports_tscinv() ? ", tscinv": ""),
     516                (supports_bmi1() ? ", bmi1" : ""),
     517                (supports_bmi2() ? ", bmi2" : ""),
     518                (supports_adx() ? ", adx" : ""));
     519   _features_str = os::strdup(buf);
     520
     521   // UseSSE is set to the smaller of what hardware supports and what
     522   // the command line requires.  I.e., you cannot set UseSSE to 2 on
     523   // older Pentiums which do not support it.
     524   if (UseSSE > 4) UseSSE=4;
     525   if (UseSSE < 0) UseSSE=0;
     526   if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
     527     UseSSE = MIN2((intx)3,UseSSE);
     528   if (!supports_sse3()) // Drop to 2 if no SSE3 support
     529     UseSSE = MIN2((intx)2,UseSSE);
     530   if (!supports_sse2()) // Drop to 1 if no SSE2 support
     531     UseSSE = MIN2((intx)1,UseSSE);
     532   if (!supports_sse ()) // Drop to 0 if no SSE  support
     533     UseSSE = 0;
     534
     535   if (UseAVX > 2) UseAVX=2;
     536   if (UseAVX < 0) UseAVX=0;
     537   if (!supports_avx2()) // Drop to 1 if no AVX2 support
     538     UseAVX = MIN2((intx)1,UseAVX);
     539   if (!supports_avx ()) // Drop to 0 if no AVX  support
     540     UseAVX = 0;
     541
     542   // Use AES instructions if available.
     543   if (supports_aes()) {
     544     if (FLAG_IS_DEFAULT(UseAES)) {
     545       UseAES = true;
     546     }
     547   } else if (UseAES) {
     548     if (!FLAG_IS_DEFAULT(UseAES))
     549       warning("AES instructions are not available on this CPU");
     550     FLAG_SET_DEFAULT(UseAES, false);
     551   }
     552
     553   // Use CLMUL instructions if available.
     554   if (supports_clmul()) {
     555     if (FLAG_IS_DEFAULT(UseCLMUL)) {
     556       UseCLMUL = true;
     557     }
     558   } else if (UseCLMUL) {
     559     if (!FLAG_IS_DEFAULT(UseCLMUL))
     560       warning("CLMUL instructions not available on this CPU (AVX may also be required)");
     561     FLAG_SET_DEFAULT(UseCLMUL, false);
     562   }
     563
     564   if (UseCLMUL && (UseSSE > 2)) {
     565     if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
     566       UseCRC32Intrinsics = true;
     567     }
     568   } else if (UseCRC32Intrinsics) {
     569     if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
     570       warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
     571     FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
     572   }
     573
     574   // The AES intrinsic stubs require AES instruction support (of course)
     575   // but also require sse3 mode for instructions it use.
     576   if (UseAES && (UseSSE > 2)) {
     577     if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
     578       UseAESIntrinsics = true;
     579     }
     580   } else if (UseAESIntrinsics) {
     581     if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
     582       warning("AES intrinsics are not available on this CPU");
     583     FLAG_SET_DEFAULT(UseAESIntrinsics, false);
     584   }
     585
     586   if (UseSHA) {
     587     warning("SHA instructions are not available on this CPU");
     588     FLAG_SET_DEFAULT(UseSHA, false);
     589   }
     590   if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
     591     warning("SHA intrinsics are not available on this CPU");
     592     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
     593     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
     594     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
     595   }
     596
     597   // Adjust RTM (Restricted Transactional Memory) flags
     598   if (!supports_rtm() && UseRTMLocking) {
     599     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
     600     // setting during arguments processing. See use_biased_locking().
     601     // VM_Version_init() is executed after UseBiasedLocking is used
     602     // in Thread::allocate().
     603     vm_exit_during_initialization("RTM instructions are not available on this CPU");
     604   }
     605
     606 #if INCLUDE_RTM_OPT
     607   if (UseRTMLocking) {
     608     if (is_intel_family_core()) {
     609       if ((_model == CPU_MODEL_HASWELL_E3) ||
     610           (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
     611           (_model == CPU_MODEL_BROADWELL  && _stepping < 4)) {
     612         if (!UnlockExperimentalVMOptions) {
     613           vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
     614         } else {
     615           warning("UseRTMLocking is only available as experimental option on this platform.");
     616         }
     617       }
     618     }
     619     if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
     620       // RTM locking should be used only for applications with
     621       // high lock contention. For now we do not use it by default.
     622       vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
     623     }
     624     if (!is_power_of_2(RTMTotalCountIncrRate)) {
     625       warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
     626       FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
     627     }
     628     if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
     629       warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
     630       FLAG_SET_DEFAULT(RTMAbortRatio, 50);
     631     }
     632   } else { // !UseRTMLocking
     633     if (UseRTMForStackLocks) {
     634       if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
     635         warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
     636       }
     637       FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
     638     }
     639     if (UseRTMDeopt) {
     640       FLAG_SET_DEFAULT(UseRTMDeopt, false);
     641     }
     642     if (PrintPreciseRTMLockingStatistics) {
     643       FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
     644     }
     645   }
     646 #else
     647   if (UseRTMLocking) {
     648     // Only C2 does RTM locking optimization.
     649     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
     650     // setting during arguments processing. See use_biased_locking().
     651     vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
     652   }
     653 #endif
     654
     655 #ifdef COMPILER2
     656   if (UseFPUForSpilling) {
     657     if (UseSSE < 2) {
     658       // Only supported with SSE2+
     659       FLAG_SET_DEFAULT(UseFPUForSpilling, false);
     660     }
     661   }
     662   if (MaxVectorSize > 0) {
     663     if (!is_power_of_2(MaxVectorSize)) {
     664       warning("MaxVectorSize must be a power of 2");
     665       FLAG_SET_DEFAULT(MaxVectorSize, 32);
     666     }
     667     if (MaxVectorSize > 32) {
     668       FLAG_SET_DEFAULT(MaxVectorSize, 32);
     669     }
     670     if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) {
     671       // 32 bytes vectors (in YMM) are only supported with AVX+
     672       FLAG_SET_DEFAULT(MaxVectorSize, 16);
     673     }
     674     if (UseSSE < 2) {
     675       // Vectors (in XMM) are only supported with SSE2+
     676       FLAG_SET_DEFAULT(MaxVectorSize, 0);
     677     }
     678 #ifdef ASSERT
     679     if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
     680       tty->print_cr("State of YMM registers after signal handle:");
     681       int nreg = 2 LP64_ONLY(+2);
     682       const char* ymm_name[4] = {"0", "7", "8", "15"};
     683       for (int i = 0; i < nreg; i++) {
     684         tty->print("YMM%s:", ymm_name[i]);
     685         for (int j = 7; j >=0; j--) {
     686           tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
     687         }
     688         tty->cr();
     689       }
     690     }
     691 #endif
     692   }
     693
     694 #ifdef _LP64
     695   if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
     696     UseMultiplyToLenIntrinsic = true;
     697   }
     698   if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
     699     UseSquareToLenIntrinsic = true;
     700   }
     701   if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
     702     UseMulAddIntrinsic = true;
     703   }
     704 #else
     705   if (UseMultiplyToLenIntrinsic) {
     706     if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
     707       warning("multiplyToLen intrinsic is not available in 32-bit VM");
     708     }
     709     FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
     710   }
     711   if (UseSquareToLenIntrinsic) {
     712     if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
     713       warning("squareToLen intrinsic is not available in 32-bit VM");
     714     }
     715     FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
     716   }
     717   if (UseMulAddIntrinsic) {
     718     if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
     719       warning("mulAdd intrinsic is not available in 32-bit VM");
     720     }
     721     FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
     722   }
     723 #endif
     724 #endif // COMPILER2
     725
     726   // On new cpus instructions which update whole XMM register should be used
     727   // to prevent partial register stall due to dependencies on high half.
     728   //
     729   // UseXmmLoadAndClearUpper == true  --> movsd(xmm, mem)
     730   // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
     731   // UseXmmRegToRegMoveAll == true  --> movaps(xmm, xmm), movapd(xmm, xmm).
     732   // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm),  movsd(xmm, xmm).
     733
     734   if( is_amd() ) { // AMD cpus specific settings
     735     if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
     736       // Use it on new AMD cpus starting from Opteron.
     737       UseAddressNop = true;
     738     }
     739     if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
     740       // Use it on new AMD cpus starting from Opteron.
     741       UseNewLongLShift = true;
     742     }
     743     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
     744       if( supports_sse4a() ) {
     745         UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
     746       } else {
     747         UseXmmLoadAndClearUpper = false;
     748       }
     749     }
     750     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
     751       if( supports_sse4a() ) {
     752         UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
     753       } else {
     754         UseXmmRegToRegMoveAll = false;
     755       }
     756     }
     757     if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
     758       if( supports_sse4a() ) {
     759         UseXmmI2F = true;
     760       } else {
     761         UseXmmI2F = false;
     762       }
     763     }
     764     if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
     765       if( supports_sse4a() ) {
     766         UseXmmI2D = true;
     767       } else {
     768         UseXmmI2D = false;
     769       }
     770     }
     771     if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) {
     772       if( supports_sse4_2() && UseSSE >= 4 ) {
     773         UseSSE42Intrinsics = true;
     774       }
     775     }
     776
     777     // some defaults for AMD family 15h
     778     if ( cpu_family() == 0x15 ) {
     779       // On family 15h processors default is no sw prefetch
     780       if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
     781         AllocatePrefetchStyle = 0;
     782       }
     783       // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
     784       if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
     785         AllocatePrefetchInstr = 3;
     786       }
     787       // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
     788       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
     789         UseXMMForArrayCopy = true;
     790       }
     791       if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
     792         UseUnalignedLoadStores = true;
     793       }
     794     }
     795
     796 #ifdef COMPILER2
     797     if (MaxVectorSize > 16) {
     798       // Limit vectors size to 16 bytes on current AMD cpus.
     799       FLAG_SET_DEFAULT(MaxVectorSize, 16);
     800     }
     801 #endif // COMPILER2
     802   }
     803
     804   if( is_intel() ) { // Intel cpus specific settings
     805     if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
     806       UseStoreImmI16 = false; // don't use it on Intel cpus
     807     }
     808     if( cpu_family() == 6 || cpu_family() == 15 ) {
     809       if( FLAG_IS_DEFAULT(UseAddressNop) ) {
     810         // Use it on all Intel cpus starting from PentiumPro
     811         UseAddressNop = true;
     812       }
     813     }
     814     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
     815       UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
     816     }
     817     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
     818       if( supports_sse3() ) {
     819         UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
     820       } else {
     821         UseXmmRegToRegMoveAll = false;
     822       }
     823     }
     824     if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
     825 #ifdef COMPILER2
     826       if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
     827         // For new Intel cpus do the next optimization:
     828         // don't align the beginning of a loop if there are enough instructions
     829         // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
     830         // in current fetch line (OptoLoopAlignment) or the padding
     831         // is big (> MaxLoopPad).
     832         // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
     833         // generated NOP instructions. 11 is the largest size of one
     834         // address NOP instruction '0F 1F' (see Assembler::nop(i)).
     835         MaxLoopPad = 11;
     836       }
     837 #endif // COMPILER2
     838       if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
     839         UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
     840       }
     841       if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
     842         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
     843           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
     844         }
     845       }
     846       if (supports_sse4_2() && UseSSE >= 4) {
     847         if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
     848           UseSSE42Intrinsics = true;
     849         }
     850       }
     851     }
     852     if ((cpu_family() == 0x06) &&
     853         ((extended_cpu_model() == 0x36) || // Centerton
     854          (extended_cpu_model() == 0x37) || // Silvermont
     855          (extended_cpu_model() == 0x4D))) {
     856 #ifdef COMPILER2
     857       if (FLAG_IS_DEFAULT(OptoScheduling)) {
     858         OptoScheduling = true;
     859       }
     860 #endif
     861       if (supports_sse4_2()) { // Silvermont
     862         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
     863           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
     864         }
     865       }
     866     }
     867     if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
     868       AllocatePrefetchInstr = 3;
     869     }
     870   }
     871
     872   // Use count leading zeros count instruction if available.
     873   if (supports_lzcnt()) {
     874     if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
     875       UseCountLeadingZerosInstruction = true;
     876     }
     877    } else if (UseCountLeadingZerosInstruction) {
     878     warning("lzcnt instruction is not available on this CPU");
     879     FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
     880   }
     881
     882   // Use count trailing zeros instruction if available
     883   if (supports_bmi1()) {
     884     // tzcnt does not require VEX prefix
     885     if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
     886       if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
     887         // Don't use tzcnt if BMI1 is switched off on command line.
     888         UseCountTrailingZerosInstruction = false;
     889       } else {
     890         UseCountTrailingZerosInstruction = true;
     891       }
     892     }
     893   } else if (UseCountTrailingZerosInstruction) {
     894     warning("tzcnt instruction is not available on this CPU");
     895     FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
     896   }
     897
     898   // BMI instructions (except tzcnt) use an encoding with VEX prefix.
     899   // VEX prefix is generated only when AVX > 0.
     900   if (supports_bmi1() && supports_avx()) {
     901     if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
     902       UseBMI1Instructions = true;
     903     }
     904   } else if (UseBMI1Instructions) {
     905     warning("BMI1 instructions are not available on this CPU (AVX is also required)");
     906     FLAG_SET_DEFAULT(UseBMI1Instructions, false);
     907   }
     908
     909   if (supports_bmi2() && supports_avx()) {
     910     if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
     911       UseBMI2Instructions = true;
     912     }
     913   } else if (UseBMI2Instructions) {
     914     warning("BMI2 instructions are not available on this CPU (AVX is also required)");
     915     FLAG_SET_DEFAULT(UseBMI2Instructions, false);
     916   }
     917
     918   // Use population count instruction if available.
     919   if (supports_popcnt()) {
     920     if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
     921       UsePopCountInstruction = true;
     922     }
     923   } else if (UsePopCountInstruction) {
     924     warning("POPCNT instruction is not available on this CPU");
     925     FLAG_SET_DEFAULT(UsePopCountInstruction, false);
     926   }
     927
     928   // Use fast-string operations if available.
     929   if (supports_erms()) {
     930     if (FLAG_IS_DEFAULT(UseFastStosb)) {
     931       UseFastStosb = true;
     932     }
     933   } else if (UseFastStosb) {
     934     warning("fast-string operations are not available on this CPU");
     935     FLAG_SET_DEFAULT(UseFastStosb, false);
     936   }
     937
     938 #ifdef COMPILER2
     939   if (FLAG_IS_DEFAULT(AlignVector)) {
     940     // Modern processors allow misaligned memory operations for vectors.
     941     AlignVector = !UseUnalignedLoadStores;
     942   }
     943 #endif // COMPILER2
     944
     945   assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
     946
     947   // set valid Prefetch instruction
     948   if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
     949   if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
     950   if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
     951   if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
     952
     953   // Allocation prefetch settings
     954   intx cache_line_size = prefetch_data_size();
     955   if( cache_line_size > AllocatePrefetchStepSize )
     956     AllocatePrefetchStepSize = cache_line_size;
     957
     958   assert(AllocatePrefetchLines > 0, "invalid value");
     959   if( AllocatePrefetchLines < 1 )     // set valid value in product VM
     960     AllocatePrefetchLines = 3;
     961   assert(AllocateInstancePrefetchLines > 0, "invalid value");
     962   if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
     963     AllocateInstancePrefetchLines = 1;
     964
     965   AllocatePrefetchDistance = allocate_prefetch_distance();
     966   AllocatePrefetchStyle    = allocate_prefetch_style();
     967
     968   if (is_intel() && cpu_family() == 6 && supports_sse3()) {
     969     if (AllocatePrefetchStyle == 2) { // watermark prefetching on Core
     970 #ifdef _LP64
     971       AllocatePrefetchDistance = 384;
     972 #else
     973       AllocatePrefetchDistance = 320;
     974 #endif
     975     }
     976     if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
     977       AllocatePrefetchDistance = 192;
     978       AllocatePrefetchLines = 4;
     979     }
     980 #ifdef COMPILER2
     981     if (supports_sse4_2()) {
     982       if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
     983         FLAG_SET_DEFAULT(UseFPUForSpilling, true);
     984       }
     985     }
     986 #endif
     987   }
     988   assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
     989
     990 #ifdef _LP64
     991   // Prefetch settings
     992   PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
     993   PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
     994   PrefetchFieldsAhead         = prefetch_fields_ahead();
     995 #endif
     996
     997   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
     998      (cache_line_size > ContendedPaddingWidth))
     999      ContendedPaddingWidth = cache_line_size;
    1000
    1001 #ifndef PRODUCT
    1002   if (PrintMiscellaneous && Verbose) {
    1003     tty->print_cr("Logical CPUs per core: %u",
    1004                   logical_processors_per_package());
    1005     tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
    1006     tty->print("UseSSE=%d", (int) UseSSE);
    1007     if (UseAVX > 0) {
    1008       tty->print("  UseAVX=%d", (int) UseAVX);
    1009     }
    1010     if (UseAES) {
    1011       tty->print("  UseAES=1");
    1012     }
    1013 #ifdef COMPILER2
    1014     if (MaxVectorSize > 0) {
    1015       tty->print("  MaxVectorSize=%d", (int) MaxVectorSize);
    1016     }
    1017 #endif
    1018     tty->cr();
    1019     tty->print("Allocation");
    1020     if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
    1021       tty->print_cr(": no prefetching");
    1022     } else {
    1023       tty->print(" prefetching: ");
    1024       if (UseSSE == 0 && supports_3dnow_prefetch()) {
    1025         tty->print("PREFETCHW");
    1026       } else if (UseSSE >= 1) {
    1027         if (AllocatePrefetchInstr == 0) {
    1028           tty->print("PREFETCHNTA");
    1029         } else if (AllocatePrefetchInstr == 1) {
    1030           tty->print("PREFETCHT0");
    1031         } else if (AllocatePrefetchInstr == 2) {
    1032           tty->print("PREFETCHT2");
    1033         } else if (AllocatePrefetchInstr == 3) {
    1034           tty->print("PREFETCHW");
    1035         }
    1036       }
    1037       if (AllocatePrefetchLines > 1) {
    1038         tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
    1039       } else {
    1040         tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
    1041       }
    1042     }
    1043
    1044     if (PrefetchCopyIntervalInBytes > 0) {
    1045       tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
    1046     }
    1047     if (PrefetchScanIntervalInBytes > 0) {
    1048       tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
    1049     }
    1050     if (PrefetchFieldsAhead > 0) {
    1051       tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
    1052     }
    1053     if (ContendedPaddingWidth > 0) {
    1054       tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
    1055     }
    1056   }
    1057 #endif // !PRODUCT
    1058 }
    1059
    1060 bool VM_Version::use_biased_locking() {
    1061 #if INCLUDE_RTM_OPT
    1062   // RTM locking is most useful when there is high lock contention and
    1063   // low data contention.  With high lock contention the lock is usually
    1064   // inflated and biased locking is not suitable for that case.
    1065   // RTM locking code requires that biased locking is off.
    1066   // Note: we can't switch off UseBiasedLocking in get_processor_features()
    1067   // because it is used by Thread::allocate() which is called before
    1068   // VM_Version::initialize().
    1069   if (UseRTMLocking && UseBiasedLocking) {
    1070     if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
    1071       FLAG_SET_DEFAULT(UseBiasedLocking, false);
    1072     } else {
    1073       warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
    1074       UseBiasedLocking = false;
    1075     }
    1076   }
    1077 #endif
    1078   return UseBiasedLocking;
    1079 }
    1080
    1081 void VM_Version::initialize() {
    1082   ResourceMark rm;
    1083   // Making this stub must be FIRST use of assembler
    1084
    1085   stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
    1086   if (stub_blob == NULL) {
    1087     vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
    1088   }
    1089   CodeBuffer c(stub_blob);
    1090   VM_Version_StubGenerator g(&c);
    1091   get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
    1092                                      g.generate_get_cpu_info());
    1093
    1094   get_processor_features();
    1095 }