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## src/cpu/x86/vm/vm_version_x86.cpp

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     678 #ifdef ASSERT
     679     if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
     680       tty->print_cr("State of YMM registers after signal handle:");
     681       int nreg = 2 LP64_ONLY(+2);
     682       const char* ymm_name[4] = {"0", "7", "8", "15"};
     683       for (int i = 0; i < nreg; i++) {
     684         tty->print("YMM%s:", ymm_name[i]);
     685         for (int j = 7; j >=0; j--) {
     686           tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
     687         }
     688         tty->cr();
     689       }
     690     }
     691 #endif
     692   }
     693
     694 #ifdef _LP64
     695   if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
     696     UseMultiplyToLenIntrinsic = true;
     697   }

     698 #else
     699   if (UseMultiplyToLenIntrinsic) {
     700     if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
     701       warning("multiplyToLen intrinsic is not available in 32-bit VM");
     702     }
     703     FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);

     704   }
     705 #endif
     706 #endif // COMPILER2
     707
     708   // On new cpus instructions which update whole XMM register should be used
     709   // to prevent partial register stall due to dependencies on high half.
     710   //
     711   // UseXmmLoadAndClearUpper == true  --> movsd(xmm, mem)
     712   // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
     713   // UseXmmRegToRegMoveAll == true  --> movaps(xmm, xmm), movapd(xmm, xmm).
     714   // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm),  movsd(xmm, xmm).
     715
     716   if( is_amd() ) { // AMD cpus specific settings
     717     if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
     718       // Use it on new AMD cpus starting from Opteron.
     719       UseAddressNop = true;
     720     }
     721     if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
     722       // Use it on new AMD cpus starting from Opteron.
     723       UseNewLongLShift = true;
     678 #ifdef ASSERT
     679     if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
     680       tty->print_cr("State of YMM registers after signal handle:");
     681       int nreg = 2 LP64_ONLY(+2);
     682       const char* ymm_name[4] = {"0", "7", "8", "15"};
     683       for (int i = 0; i < nreg; i++) {
     684         tty->print("YMM%s:", ymm_name[i]);
     685         for (int j = 7; j >=0; j--) {
     686           tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
     687         }
     688         tty->cr();
     689       }
     690     }
     691 #endif
     692   }
     693
     694 #ifdef _LP64
     695   if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
     696     UseMultiplyToLenIntrinsic = true;
     697   }
     698   if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
     699     UseSquareToLenIntrinsic = true;
     700   }
     701   if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
     702     UseMulAddIntrinsic = true;
     703   }
     704 #else
     705   if (UseMultiplyToLenIntrinsic) {
     706     if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
     707       warning("multiplyToLen intrinsic is not available in 32-bit VM");
     708     }
     709     FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
     710   }
     711   if (UseSquareToLenIntrinsic) {
     712     if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
     713       warning("squareToLen intrinsic is not available in 32-bit VM");
     714     }
     715     FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
     716   }
     717   if (UseMulAddIntrinsic) {
     718     if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
     719       warning("mulAdd intrinsic is not available in 32-bit VM");
     720     }
     721     FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
     722   }
     723 #endif
     724 #endif // COMPILER2
     725
     726   // On new cpus instructions which update whole XMM register should be used
     727   // to prevent partial register stall due to dependencies on high half.
     728   //
     729   // UseXmmLoadAndClearUpper == true  --> movsd(xmm, mem)
     730   // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
     731   // UseXmmRegToRegMoveAll == true  --> movaps(xmm, xmm), movapd(xmm, xmm).
     732   // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm),  movsd(xmm, xmm).
     733
     734   if( is_amd() ) { // AMD cpus specific settings
     735     if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
     736       // Use it on new AMD cpus starting from Opteron.
     737       UseAddressNop = true;
     738     }
     739     if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
     740       // Use it on new AMD cpus starting from Opteron.
     741       UseNewLongLShift = true;

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