diff --git a/src/hotspot/cpu/aarch64/aarch64.ad b/src/hotspot/cpu/aarch64/aarch64.ad
index f1dcc0443c6..c9d1d6d394f 100644
--- a/src/hotspot/cpu/aarch64/aarch64.ad
+++ b/src/hotspot/cpu/aarch64/aarch64.ad
@@ -804,6 +804,10 @@ reg_class fp_reg(
     R29, R29_H
 );
 
+reg_class r29(
+    R29
+);
+
 // Class for link register
 reg_class lr_reg(
     R30, R30_H
@@ -5339,6 +5343,17 @@ operand iRegN()
   interface(REG_INTER);
 %}
 
+// Pointer Register Operands
+// Narrow Pointer Register
+operand iRegNFP()
+%{
+  constraint(ALLOC_IN_RC(r29));
+  match(RegN);
+  op_cost(0);
+  format %{ %}
+  interface(REG_INTER);
+%}
+
 operand iRegN_R0()
 %{
   constraint(ALLOC_IN_RC(r0_reg));
@@ -7632,15 +7647,25 @@ instruct loadP(iRegPNoSp dst, memory8 mem)
 %}
 
 // Load Compressed Pointer
-instruct loadN(iRegNNoSp dst, memory4 mem)
+instruct loadN(iRegNNoSp dst, iRegNFP tmp, memory4 mem)
 %{
   match(Set dst (LoadN mem));
   predicate(!needs_acquiring_load(n));
+  effect(TEMP tmp);
 
   ins_cost(4 * INSN_COST);
-  format %{ "ldrw  $dst, $mem\t# compressed ptr" %}
+  format %{
+      "$tmp = 2 # trash reg"
+      "\n\t"
+      "ldrw  $dst, $mem\t# compressed ptr"
+  %}
 
-  ins_encode(aarch64_enc_ldrw(dst, mem));
+  ins_encode %{
+    __ mov($tmp$$Register, 2);
+    Register dst_reg = as_Register($dst$$reg);
+    loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldrw, dst_reg, $mem->opcode(),
+               as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
+  %}
 
   ins_pipe(iload_reg_mem);
 %}