ARM: C2: matcher causes sub-optimal code for ARM

On arm32 and arm64, expressions like AddP (LShiftL (IConvI2L src1) src2) can be
done in a single ADD instruction. However, when the matcher sees that the
LShiftL is "shared", it forces it into a register. So instead of getting

  ADD R_R6,R_R0,R_R1 sxtw #3
  FLDD R_V8,[R_R6 + #16]
  ADD R_R4,R_R2,R_R1 sxtw #3
[...]
  FSTD R_V10,[R_R4 + #16]

we end up with:

 SXTW R_R4,R_R1 ! int->long
 LSL R_R4,R_R4,#3 ! long
 ADD R_R6,R_R0,R_R4 ! ptr
 FLDD R_V8,[R_R6 + #16]
 ADD R_R4,R_R2,R_R4 ! ptr
[...]
 FSTD R_V10,[R_R4 + #16]