Backports
Issue | Fix Version | Assignee | Priority | Status | Resolution | Resolved In Build |
---|---|---|---|---|---|---|
JDK-8311706 | 17.0.9 | Fei Yang | P5 | Resolved | Fixed | b01 |
Description
On behalf of Dingli Zhang (dingli@iscas.ac.cn)
In riscv, 'imm[31:28]’ should be 'imm[31:20]' for '0x7ff' in the following two places:
src/hotspot/cpu/riscv/assembler_riscv.cpp:
```
void Assembler::li64(Register Rd, int64_t imm) {
// Load upper 32 bits. upper = imm[63:32], but if imm[31] == 1 or
// (imm[31:28] == 0x7ff && imm[19] == 1), upper = imm[63:32] + 1.
int64_t lower = imm & 0xffffffff;
```
src/hotspot/cpu/riscv/macroAssembler_riscv.cpp:
```
// Load upper 32 bits. Upper = target[63:32], but if target[31] = 1 or (target[31:28] == 0x7ff && target[19] == 1),
// upper = target[63:32] + 1.
```
In riscv, 'imm[31:28]’ should be 'imm[31:20]' for '0x7ff' in the following two places:
src/hotspot/cpu/riscv/assembler_riscv.cpp:
```
void Assembler::li64(Register Rd, int64_t imm) {
// Load upper 32 bits. upper = imm[63:32], but if imm[31] == 1 or
// (imm[31:28] == 0x7ff && imm[19] == 1), upper = imm[63:32] + 1.
int64_t lower = imm & 0xffffffff;
```
src/hotspot/cpu/riscv/macroAssembler_riscv.cpp:
```
// Load upper 32 bits. Upper = target[63:32], but if target[31] = 1 or (target[31:28] == 0x7ff && target[19] == 1),
// upper = target[63:32] + 1.
```