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Type:
Enhancement
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Resolution: Fixed
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Priority:
P4
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Affects Version/s: 9
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Component/s: core-libs
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b13
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x86
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generic
Transactional memory performance is improved if field updates to the same cache line occur late in the transaction and are not separated by conditional logic.
- relates to
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JDK-8031320 Use Intel RTM instructions for locks
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- Closed
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