Normally in make, targets are only rebuilt if one of the sources, or prerequisites, have changed. This usually works pretty well. However, there are cases where a change in a makefile, or in the configuration, should trigger a rebuild of certain targets. Some example of these cases are:

* A compiler flag has changed.
* Version string has changed and is generated into a source file or -D flag.
* The compiler itself has changed.

To fix this, I propose creating a macro that would be used like this. Consider the following rule and recipe:

/path/to/some/target-file: /path/to/some/source-file
        $(SED) -e 's/foo/$(SOME_VARIABLE)/g' < $< > $@

If the value of SOME_VARIABLE changed, but not the source file, it would not get rebuilt, but if we add a call to the macro like this:

/path/to/some/target-file: /path/to/some/source-file $(call DependOnVariable, SOME_VARIABLE)
        $(SED) -e 's/foo/$(SOME_VARIABLE)/g' < $< > $@

The recipe would get rerun if the variable had changed since last the recipe was run.

This would be accomplished by printing the value of the variable to a special file under make-support in the output dir. The contents of this file would then be compared to the value of the variable. If they differ, the file is updated with the new value. The macro returns the name of the file, which becomes a prerequisite tot he rule. So, if the file is updated (this happens in the parsing phase of make), it will trigger the rule to run the recipe.

With this macro available, we can add usage of it to all the Setup* macros we already have, like SetupNativeCompilation. We will need to be careful though so we do not apply it with too fine granularity, as the cost of checking the file for variable changes can get expensive if used too liberally.