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Enhancement
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Resolution: Unresolved
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P3
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9, 10
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arm
Arm32 and arm64 can spill to FP registers, thanks to this code:
ifdef ARM
// ARM has support for moving 64bit values between a pair of
// integer registers and a double register
idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
#endif
however, this increases and FP register pressure and VMOV is slower than a load or store on arm64 (and probably armv7 arm32) because of the FP pipeline.
ifdef ARM
// ARM has support for moving 64bit values between a pair of
// integer registers and a double register
idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
#endif
however, this increases and FP register pressure and VMOV is slower than a load or store on arm64 (and probably armv7 arm32) because of the FP pipeline.