Some time ago, we implemented support for ordering of "Independent Reads of Independent Writes" in the template interpreter and C2 Compiler for PPC64. However, it needs to be consistent with C1.
Without "IRIW" support, we generate load-acquire for volatile loads and release-store-fence for volatile stores.
With "IRIW" support, we generate fence-load-acquire for volatile loads and release-store for volatile stores. CPU_NOT_MULTIPLE_COPY_ATOMIC is currently only defined on PPC64 (though it may be interesting for aarch64 as well).
This change is a prerequisite for our C1 on PPC64 contribution.
Without "IRIW" support, we generate load-acquire for volatile loads and release-store-fence for volatile stores.
With "IRIW" support, we generate fence-load-acquire for volatile loads and release-store for volatile stores. CPU_NOT_MULTIPLE_COPY_ATOMIC is currently only defined on PPC64 (though it may be interesting for aarch64 as well).
This change is a prerequisite for our C1 on PPC64 contribution.
- duplicates
-
JDK-8032366 Implement C1 support for IRIW conformance on non-multiple-copy-atomic platforms
-
- Closed
-
- relates to
-
JDK-8029101 PPC64 (part 211): ordering of Independent Reads of Independent Writes
-
- Resolved
-