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Bug
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Resolution: Fixed
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P4
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port-stage-aarch32-8, port-stage-aarch32-9
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aarch32
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linux
The problem is in calculating the offset where SIGSEGV that should be turned into NPE can happen.
Before introducing ldrd/strd macrosses in macroAssembler we could rely on code_offset() saved before emitting load/store operation.
However now in case several address modes ldrd/strd macrosses will emit an additional instruction resolving address before real load/store.
The code offset where implicit NPE can happen now can be calculated by sum of code_offset() and value returned by ldrd/strd macrosess.
Before introducing ldrd/strd macrosses in macroAssembler we could rely on code_offset() saved before emitting load/store operation.
However now in case several address modes ldrd/strd macrosses will emit an additional instruction resolving address before real load/store.
The code offset where implicit NPE can happen now can be calculated by sum of code_offset() and value returned by ldrd/strd macrosess.