The aarch64 port implicitly transforms:
(AddP base (AddP base address (LShiftL index con)) offset)
into:
(AddP base (AddP base offset) (LShiftL index con))
in the ad file to embed the shift (and possibly and i2l conversion) into the addressing mode of a memory operation. Exposing that transformation in the ideal graph allows:
- (AddP base offset) to be scheduled (for instance outside a loop)
- multiple identical (AddP base offset) can be commoned
- (LShiftL index con) can be cloned during matching so that each memory access has its own
(AddP base (AddP base address (LShiftL index con)) offset)
into:
(AddP base (AddP base offset) (LShiftL index con))
in the ad file to embed the shift (and possibly and i2l conversion) into the addressing mode of a memory operation. Exposing that transformation in the ideal graph allows:
- (AddP base offset) to be scheduled (for instance outside a loop)
- multiple identical (AddP base offset) can be commoned
- (LShiftL index con) can be cloned during matching so that each memory access has its own
- relates to
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JDK-8267689 [8u] [aarch64] Crash due to bad shift in indirect addressing mode
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- Resolved
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JDK-8068350 ARM: C2: matcher causes sub-optimal code for ARM
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- Open
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- Resolved
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- Open
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