Issue | Fix Version | Assignee | Priority | Status | Resolution | Resolved In Build |
---|---|---|---|---|---|---|
JDK-8174406 | 10 | Martin Doerr | P2 | Resolved | Fixed | b01 |
JDK-8183656 | 8u161 | Martin Doerr | P2 | Resolved | Fixed | b01 |
JDK-8172257 | 8u152 | Martin Doerr | P2 | Closed | Fixed | b01 |
JDK-8192219 | emb-8u161 | Martin Doerr | P2 | Resolved | Fixed | b01 |
C2 compiler has generated incorrect code on PPC64 for the following method:
java/awt/Component.setBackground(Ljava/awt/Color;)V
It starts with the following accesses:
Color oldColor = background; // oop load from field "background"
ComponentPeer peer = this.peer; // volatile load from other field
background = c; // oop store to field "background"
Note that we use support_IRIW_for_not_multiple_copy_atomic_cpu = true on PPC64 which has the effect, that the volatile load is preceded by a MemBarVolatile.
That's why the mach graph looks like this after matching (simplified, only showing memory dependencies):
1: MachProj Memory
2: loadN2P_unscaled(1) // oldColor = background
3: membar_volatile(1)
4: MachProj(3)
5: loadN_ac(4) // peer = this.peer
6: unnecessary_membar_acquire(4)
7: MachProj(6)
8: storeN(7) // background = c
PhaseCFG::insert_anti_dependences must find an anti-dependence between 8 and 2 in order to schedule the load correctly.
Because insert_anti_dependences does not follow memory edges behind membars, this does not happen and the load gets executed after the store and hence returns the already overwritten value.
The code contains a comment "Wide MemBar's are anti-dependent on everything (except immutable memories).", but a check for this case is missing.
The membar's adr_type is NULL so can_alias returns false and reordering is not prevented.
java/awt/Component.setBackground(Ljava/awt/Color;)V
It starts with the following accesses:
Color oldColor = background; // oop load from field "background"
ComponentPeer peer = this.peer; // volatile load from other field
background = c; // oop store to field "background"
Note that we use support_IRIW_for_not_multiple_copy_atomic_cpu = true on PPC64 which has the effect, that the volatile load is preceded by a MemBarVolatile.
That's why the mach graph looks like this after matching (simplified, only showing memory dependencies):
1: MachProj Memory
2: loadN2P_unscaled(1) // oldColor = background
3: membar_volatile(1)
4: MachProj(3)
5: loadN_ac(4) // peer = this.peer
6: unnecessary_membar_acquire(4)
7: MachProj(6)
8: storeN(7) // background = c
PhaseCFG::insert_anti_dependences must find an anti-dependence between 8 and 2 in order to schedule the load correctly.
Because insert_anti_dependences does not follow memory edges behind membars, this does not happen and the load gets executed after the store and hence returns the already overwritten value.
The code contains a comment "Wide MemBar's are anti-dependent on everything (except immutable memories).", but a check for this case is missing.
The membar's adr_type is NULL so can_alias returns false and reordering is not prevented.
- backported by
-
JDK-8174406 C2: anti dependence missed because store hidden by membar
- Resolved
-
JDK-8183656 C2: anti dependence missed because store hidden by membar
- Resolved
-
JDK-8192219 C2: anti dependence missed because store hidden by membar
- Resolved
-
JDK-8172257 C2: anti dependence missed because store hidden by membar
- Closed
- relates to
-
JDK-8172850 Anti-dependency on membar causes crash in register allocator due to invalid instruction scheduling
- Closed