INC and DEC are two of most frequently encountered instructions that can suffer from unexpected performance drops on processors which don't optimize for partial write flags. Compiler should use ADD 0x1 or SUB 0x1 instead on these CPUs to avoid potential partial flag stalls during execution. This optimization disables generation of INC and DEC instructions for Knights family and Slivermont ATOM based processors. We observed 3.65% gain on SPECjvm2008 composite score on Knights Landing (KNL) platform.
Code contributed by: Rahul Kandu (rahul.kandu@intel.com)