This change contains a row of minor improvements to the x86 and sparc platform ports. Most of these have already been contributed with the ppc and s390 ports.
 
Move null check info before load LIR_Assembler::emit_alloc_obj. Doesn't make sense after it where it was followed by a non-storage access instruction.

C1 on x86: Fix for assertion hit when running with -XX:-ImplicitDiv0Checks
Symptom1: assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions");
Symptom2: DivByZeroStub was emitted twice per idiv/irem
Fix1: create the lir_idiv without debug info (CodeEmitInfo*). When running with -XX:-ImplicitDiv0Checks the actual idiv cannot trap or reach a safepoint.
Fix2: don't call add_debug_info_for_div0() in the lir assembler. It adds another DivByZeroStub to the stub list.

compiledIC:
Data / destination can be reloaded if not volatile causing assertion to fire.

stub_Generator:
A small optimization for G1: Only call static_write_ref_array_pre from array copy stubs if G1 marking is active.