In C1 backend, the div/rem by power-of-2 optimization for AArch64 is missing.

There're two LIR_Assembler::arithmetic_idiv() methods in c1_LIRAssembler_aarch64.cpp, one is left unimplemented, the other tried to check whether the divisor is power-of-2 but did nothing optimized then.

Currently, C1 generates below assembly for (x / 8)

0x0000ffff7d593354: orr w0, wzr, #0x8
0x0000ffff7d593358: cmp x0, #0x0
0x0000ffff7d59335c: b.eq 0x0000ffff7d59337c // b.none
0x0000ffff7d593360: sdiv w1, w1, w0
and below assembly for (x % 8)

0x0000ffff91593354: orr w0, wzr, #0x8
0x0000ffff91593358: cmp x0, #0x0
0x0000ffff9159335c: b.eq 0x0000ffff91593380 // b.none
0x0000ffff91593360: sdiv w8, w1, w0
0x0000ffff91593364: msub w1, w8, w0, w1
But in all the other architectures, C1 backend can generate more optimized code. AArch64 should include at least two optimizations:

remove the div-by-zero check if the divisor is known to be a non-zero constant
use inexpensive instructions instead of the sdiv to do div/rem by power-of-2 constant