On 3/04/2019 5:20 pm, Jinke Fan wrote:
> Hello All,
>
> This patch is used to support Hygon Dhyana x86 vendor id (HygonGenuine).
> As Hygon Dhyana CPU share most architecture feature same as AMD Family 17h, the patch adds Hygon CPU Vendor ID check to reuse AMD code paths.
>
> Background:
> Chengdu Haiguang IC Design Co., Ltd (Hygon) is a Joint Venture
> between AMD and Haiguang Information Technology Co.,Ltd., aims at
> providing high performance x86 processor for China server market.
> Its first generation processor codename is Dhyana, which
> originates from AMD technology and shares most of the
> architecture with AMD's family 17h, but with different CPU Vendor
> ID("HygonGenuine")/Family series number(Family 18h).
>
> The patch is based on the original repository:
> hg.openjdk.java.net/jdk/jdk
>
> changeset: 54384:cd3b7ad53265
> tag: tip
> user: kvn
> date: Tue Apr 02 09:45:52 2019 -0700
> summary: 8221782: [Graal] Module jdk.internal.vm.compiler.management has not been granted accessClassInPackage.jdk.vm.ci.services
>
> Please help me with the commit process.
> Thank you very much!
>
> *patch
> Webrev:
> https://fjkbo.github.io/openjdk/webrev/index.html
>
> The output of hg diff -g:
> diff --git a/src/hotspot/cpu/x86/assembler_x86.cpp b/src/hotspot/cpu/x86/assembler_x86.cpp
> --- a/src/hotspot/cpu/x86/assembler_x86.cpp
> +++ b/src/hotspot/cpu/x86/assembler_x86.cpp
> @@ -3099,7 +3099,7 @@
> }
> return;
> }
> - if (UseAddressNop && VM_Version::is_amd()) {
> + if (UseAddressNop && (VM_Version::is_amd() || VM_Version::is_hygon())) {
> //
> // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
> // 1: 0x90
> diff --git a/src/hotspot/cpu/x86/vm_version_ext_x86.cpp b/src/hotspot/cpu/x86/vm_version_ext_x86.cpp
> --- a/src/hotspot/cpu/x86/vm_version_ext_x86.cpp
> +++ b/src/hotspot/cpu/x86/vm_version_ext_x86.cpp
> @@ -340,6 +340,10 @@
> return !is_amd_Barcelona();
> }
>
> + if (is_hygon()) {
> + return true;
> + }
> +
> return false;
> }
>
> diff --git a/src/hotspot/cpu/x86/vm_version_x86.cpp b/src/hotspot/cpu/x86/vm_version_x86.cpp
> --- a/src/hotspot/cpu/x86/vm_version_x86.cpp
> +++ b/src/hotspot/cpu/x86/vm_version_x86.cpp
> @@ -1165,7 +1165,7 @@
> }
> }
>
> - if( is_amd() ) { // AMD cpus specific settings
> + if( is_amd() || is_hygon() ) { // AMD cpus specific settings
> if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
> // Use it on new AMD cpus starting from Opteron.
> UseAddressNop = true;
> @@ -1239,8 +1239,8 @@
> }
> #endif // COMPILER2
>
> - // Some defaults for AMD family 17h
> - if ( cpu_family() == 0x17 ) {
> + // Some defaults for AMD family 17h || Hygon family 18h
> + if ( cpu_family() == 0x17 || cpu_family() == 0x18 ) {
> // On family 17h processors use XMM and UnalignedLoadStores for Array Copy
> if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
> FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
> diff --git a/src/hotspot/cpu/x86/vm_version_x86.hpp b/src/hotspot/cpu/x86/vm_version_x86.hpp
> --- a/src/hotspot/cpu/x86/vm_version_x86.hpp
> +++ b/src/hotspot/cpu/x86/vm_version_x86.hpp
> @@ -495,13 +495,13 @@
> result |= CPU_CX8;
> if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
> result |= CPU_CMOV;
> - if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
> + if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || ((is_amd() || is_hygon()) &&
> _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
> result |= CPU_FXSR;
> // HT flag is set for multi-core processors also.
> if (threads_per_core() > 1)
> result |= CPU_HT;
> - if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() &&
> + if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || ((is_amd() || is_hygon()) &&
> _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
> result |= CPU_MMX;
> if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
> @@ -576,8 +576,8 @@
> if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
> result |= CPU_FMA;
>
> - // AMD features.
> - if (is_amd()) {
> + // AMD|Hygon features.
> + if (is_amd() || is_hygon()) {
> if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
> (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
> result |= CPU_3DNOW_PREFETCH;
> @@ -711,6 +711,7 @@
> static int cpu_family() { return _cpu;}
> static bool is_P6() { return cpu_family() >= 6; }
> static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
> + static bool is_hygon() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x6F677948; } // 'ogyH'
> static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
> static bool is_zx() { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS '
> static bool is_atom_family() { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x36) || (extended_cpu_model() == 0x37) || (extended_cpu_model() == 0x4D))); } //Silvermont and Centerton
> @@ -734,7 +735,7 @@
> if (!supports_topology || result == 0) {
> result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
> }
> - } else if (is_amd()) {
> + } else if (is_amd() || is_hygon()) {
> result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
> } else if (is_zx()) {
> bool supports_topology = supports_processor_topology();
> @@ -770,7 +771,7 @@
> intx result = 0;
> if (is_intel()) {
> result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
> - } else if (is_amd()) {
> + } else if (is_amd() || is_hygon()) {
> result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
> } else if (is_zx()) {
> result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
> @@ -857,7 +858,7 @@
>
> // AMD features
> static bool supports_3dnow_prefetch() { return (_features & CPU_3DNOW_PREFETCH) != 0; }
> - static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
> + static bool supports_mmx_ext() { return (is_amd()||is_hygon()) && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
> static bool supports_lzcnt() { return (_features & CPU_LZCNT) != 0; }
> static bool supports_sse4a() { return (_features & CPU_SSE4A) != 0; }
>
> @@ -870,7 +871,7 @@
> }
> static bool supports_tscinv() {
> return supports_tscinv_bit() &&
> - ( (is_amd() && !is_amd_Barcelona()) ||
> + ( ((is_amd()||is_hygon()) && !is_amd_Barcelona()) ||
> is_intel_tsc_synched_at_init() );
> }
>
> @@ -896,7 +897,7 @@
> // Core - 256 / prefetchnta
> // It will be used only when AllocatePrefetchStyle > 0
>
> - if (is_amd()) { // AMD
> + if (is_amd() || is_hygon()) { // AMD
> if (supports_sse2()) {
> return 256; // Opteron
> } else {
>
> *test
> I tested it with jtreg and found no regressions.
>
> Base Run：
> ==============================
> Test summary
> ==============================
> TEST TOTAL PASS FAIL ERROR
> jtreg:test/hotspot/jtreg:tier1 1396 1396 0 0
>>> jtreg:test/jdk:tier1 1867 1866 1 0 <<
>>> jtreg:test/langtools:tier1 3920 3919 1 0 <<
> jtreg:test/nashorn:tier1 0 0 0 0
> jtreg:test/jaxp:tier1 0 0 0 0
> ==============================
> TEST FAILURE
>
> And The result of after patching is the same as the before.
> ==============================
> Test summary
> ==============================
> TEST TOTAL PASS FAIL ERROR
> jtreg:test/hotspot/jtreg:tier1 1396 1396 0 0
>>> jtreg:test/jdk:tier1 1867 1866 1 0 <<
>>> jtreg:test/langtools:tier1 3920 3919 1 0 <<
> jtreg:test/nashorn:tier1 0 0 0 0
> jtreg:test/jaxp:tier1 0 0 0 0
> ==============================
> TEST FAILURE
>
> Is there anything incorrectly?
> Please let me know your comments.
>
> Best Regards!
> Fanjinke.