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Enhancement
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Resolution: Fixed
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P2
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14
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x86
Different clauses of instruction pattern are compiled by ADLC to generate code catering to different stages in the compilation. This multiplicity in patterns for the same operation meagerly differing in vector operands translates to the generation of lots of extra functional and conditional logic which effectivity increases the libjvm.so size.
Collapsing such multiple patterns to one pattern should not only help in size reduction of generated object files but also help in better maintenance and cleanup of AD files
- is blocked by
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JDK-8234391 C2: Generic vector operands
- Resolved
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JDK-8234392 C2: Extend Matcher::match_rule_supported_vector() with element type information
- Resolved
- relates to
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JDK-8234394 C2: Dynamic register class support in ADLC
- Resolved
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JDK-8235824 C2: Merge AD instructions for AddReductionV and MulReductionV nodes
- Resolved
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JDK-8235825 C2: Merge AD instructions for Replicate nodes
- Resolved
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JDK-8229866 [vector] Reduce code size generated from AD files
- Open
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JDK-8235405 C2: Merge AD instructions for different vector operations
- Resolved
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JDK-8235688 C2: Merge AD instructions for AddV, SubV, and MulV nodes
- Resolved
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JDK-8235719 C2: Merge AD instructions for ShiftV, AbsV, and NegV nodes
- Resolved
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JDK-8235756 C2: Merge AD instructions for DivV, SqrtV, and FmaV nodes
- Resolved