C1 and C2 compiler contain code to insert a release barrier for constructors which write volatile fields.
This is only relevant for platforms with the property "support_IRIW_for_not_multiple_copy_atomic_cpu", currently only PPC64. Other platforms already add a heavy-weight memory barrier after each volatile store.
The implementation is not consistent:
C1 GraphBuilder::method_return uses:
support_IRIW_for_not_multiple_copy_atomic_cpu && scope()->wrote_volatile()
C2 Parse::do_exits() uses:
PPC64_ONLY(wrote_volatile())
This is currently not an issue, but should better be made consistent to avoid inconsistencies for future changes.
This is only relevant for platforms with the property "support_IRIW_for_not_multiple_copy_atomic_cpu", currently only PPC64. Other platforms already add a heavy-weight memory barrier after each volatile store.
The implementation is not consistent:
C1 GraphBuilder::method_return uses:
support_IRIW_for_not_multiple_copy_atomic_cpu && scope()->wrote_volatile()
C2 Parse::do_exits() uses:
PPC64_ONLY(wrote_volatile())
This is currently not an issue, but should better be made consistent to avoid inconsistencies for future changes.
- relates to
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JDK-8229422 Taskqueue: Outdated selection of weak memory model platforms
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- Resolved
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