Discussion Thread: https://mail.openjdk.java.net/pipermail/aarch64-port-dev/2019-November/008164.html

The current implementation of aarch64 atomic operations depends on the version of the GCC compiler used. The code sequence may not be expected with a certain version of GCC compiler. As a result, full memory barrier are not ensured for memory_order_conservative.

Patch:
diff -r dc45ed0ab083 src/hotspot/os_cpu/linux_aarch64/atomic_linux_aarch64.hpp
--- a/src/hotspot/os_cpu/linux_aarch64/atomic_linux_aarch64.hpp Wed Nov 13 15:16:45 2019 -0800
+++ b/src/hotspot/os_cpu/linux_aarch64/atomic_linux_aarch64.hpp Thu Nov 14 09:26:49 2019 +0800
@@ -29,6 +29,8 @@
 #include "vm_version_aarch64.hpp"

 // Implementation of class atomic
+// Note that memory_order_conservative requires a full barrier after atomic stores.
+// See https://patchwork.kernel.org/patch/3575821/

 #define FULL_MEM_BARRIER __sync_synchronize()
 #define READ_MEM_BARRIER __atomic_thread_fence(__ATOMIC_ACQUIRE);
@@ -52,7 +54,7 @@
                                                      T volatile* dest,
                                                      atomic_memory_order order) const {
   STATIC_ASSERT(byte_size == sizeof(T));
- T res = __sync_lock_test_and_set(dest, exchange_value);
+ T res = __atomic_exchange_n(dest, exchange_value, __ATOMIC_RELEASE);
   FULL_MEM_BARRIER;
   return res;
 }
@@ -70,7 +72,12 @@
                               __ATOMIC_RELAXED, __ATOMIC_RELAXED);
     return value;
   } else {
- return __sync_val_compare_and_swap(dest, compare_value, exchange_value);
+ T value = compare_value;
+ FULL_MEM_BARRIER;
+ __atomic_compare_exchange(dest, &value, &exchange_value, /*weak*/false,
+ __ATOMIC_RELAXED, __ATOMIC_RELAXED);
+ FULL_MEM_BARRIER;
+ return value;
   }
 }