Witnessed some random assembler warnings when executing aarch64-asmtest.py script.
$ python ./src/hotspot/cpu/aarch64/aarch64-asmtest.py | grep Warning
aarch64ops.s: Assembler messages:
aarch64ops.s:424: Warning: unpredictable load of register pair -- `ldpsw x10,x10,[x9,#-32]'
aarch64ops.s:428: Warning: unpredictable transfer with writeback -- `stp w30,w12,[x30,#-256]!'
aarch64ops.s:435: Warning: unpredictable transfer with writeback -- `ldp w4,w23,[x4],#-112'
aarch64ops.s:221: Warning: unpredictable transfer with writeback -- `str x6,[x6,11]!'
aarch64ops.s:223: Warning: unpredictable transfer with writeback -- `strb w0,[x0,-8]!'
We should avoid this kind of noise. This could be fixed by the following fix:
diff -r ff84f0491003 src/hotspot/cpu/aarch64/aarch64-asmtest.py
--- a/src/hotspot/cpu/aarch64/aarch64-asmtest.py Sat Aug 15 18:13:49 2020 -0700
+++ b/src/hotspot/cpu/aarch64/aarch64-asmtest.py Mon Aug 17 09:40:12 2020 +0800
@@ -741,6 +741,11 @@
regMode = FloatRegister if isFloat else GeneralRegister
self.reg = regMode().generate()
+
+ kindStr = Address.kindToStr(self.kind);
+ if (not isFloat) and (kindStr is "pre" or kindStr is "post"):
+ (self.reg.number, self.adr.base.number) = random.sample(range(31), 2)
+
return self
def cstr(self):
@@ -777,6 +782,16 @@
self.reg = [OperandFactory.create(self.mode).generate()
for i in range(self.numRegs)]
self.base = OperandFactory.create('x').generate()
+
+ kindStr = Address.kindToStr(self.kind);
+ if kindStr is "pre" or kindStr is "post":
+ if self._name.startswith("ld"):
+ (self.reg[0].number, self.reg[1].number, self.base.number) = random.sample(range(31), 3)
+ if self._name.startswith("st"):
+ self.base.number = random.choice(list(set(range(31)) - set([self.reg[0].number, self.reg[1].number])))
+ elif self._name.startswith("ld"):
+ (self.reg[0].number, self.reg[1].number) = random.sample(range(31), 2)
+
return self
def astr(self):
$ python ./src/hotspot/cpu/aarch64/aarch64-asmtest.py | grep Warning
aarch64ops.s: Assembler messages:
aarch64ops.s:424: Warning: unpredictable load of register pair -- `ldpsw x10,x10,[x9,#-32]'
aarch64ops.s:428: Warning: unpredictable transfer with writeback -- `stp w30,w12,[x30,#-256]!'
aarch64ops.s:435: Warning: unpredictable transfer with writeback -- `ldp w4,w23,[x4],#-112'
aarch64ops.s:221: Warning: unpredictable transfer with writeback -- `str x6,[x6,11]!'
aarch64ops.s:223: Warning: unpredictable transfer with writeback -- `strb w0,[x0,-8]!'
We should avoid this kind of noise. This could be fixed by the following fix:
diff -r ff84f0491003 src/hotspot/cpu/aarch64/aarch64-asmtest.py
--- a/src/hotspot/cpu/aarch64/aarch64-asmtest.py Sat Aug 15 18:13:49 2020 -0700
+++ b/src/hotspot/cpu/aarch64/aarch64-asmtest.py Mon Aug 17 09:40:12 2020 +0800
@@ -741,6 +741,11 @@
regMode = FloatRegister if isFloat else GeneralRegister
self.reg = regMode().generate()
+
+ kindStr = Address.kindToStr(self.kind);
+ if (not isFloat) and (kindStr is "pre" or kindStr is "post"):
+ (self.reg.number, self.adr.base.number) = random.sample(range(31), 2)
+
return self
def cstr(self):
@@ -777,6 +782,16 @@
self.reg = [OperandFactory.create(self.mode).generate()
for i in range(self.numRegs)]
self.base = OperandFactory.create('x').generate()
+
+ kindStr = Address.kindToStr(self.kind);
+ if kindStr is "pre" or kindStr is "post":
+ if self._name.startswith("ld"):
+ (self.reg[0].number, self.reg[1].number, self.base.number) = random.sample(range(31), 3)
+ if self._name.startswith("st"):
+ self.base.number = random.choice(list(set(range(31)) - set([self.reg[0].number, self.reg[1].number])))
+ elif self._name.startswith("ld"):
+ (self.reg[0].number, self.reg[1].number) = random.sample(range(31), 2)
+
return self
def astr(self):