G1 x86 C1/Interpreter post write barrier always uses 32 bit to access variable sized PtrQueue::_index

On x86 ther c1/interpreter post write barrier always uses 32 bit accesses to access the PtrQueue::_index parameter although it's a size_t.

Particular this code:

  __ cmpl(queue_index, 0); // fixed 32 bit read/comparison
  __ jcc(Assembler::equal, runtime);
  __ subl(queue_index, wordSize); // fixed 32 bit subtraction
  __ movptr(tmp2, buffer);
#ifdef _LP64
  __ movslq(rscratch1, queue_index); // fixed 32 bit read + sign extension(?)
  __ addq(tmp2, rscratch1);
  __ movq(Address(tmp2, 0), card_addr);
#else

is wrong. The pre-write barrier is fine, and cursory look through other architectures the code used is fine too.

This is no real issue due to endianess and the index never > 2^31.