AArch64: Fix reinterpretX2D match rule issue

This is a similar issue with https://bugs.openjdk.java.net/browse/JDK-8259353.
Currently on AArch64 NEON, the match rule of “reinterpretX2D" which implements the vector reinterpret from 16 bytes to 8 bytes, doesn't generate any register move instruction if the 'dst' and 'src' are the same register. This is not right since the higher 64-bits of the dst register can not be cleared to zero, which is not expected.

See the codes:
  instruct reinterpretX2D(vecD dst, vecX src)
  %{
    predicate(n->bottom_type()->is_vect()->length_in_bytes() == 8 &&
                    n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 16);
    match(Set dst (VectorReinterpret src));
    ins_cost(INSN_COST);
    format %{ " # reinterpret $dst,$src" %}
    ins_encode %{
      // If register is the same, then move is not needed.
      if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
        __ orr(as_FloatRegister($dst$$reg), __ T8B,
                  as_FloatRegister($src$$reg),
                  as_FloatRegister($src$$reg));
       }
    %}
    ins_pipe(vlogical64);
  %}

This might lead the same issue with https://bugs.openjdk.java.net/browse/JDK-8259353.