The aarch64 LSE atomic operations are introduced to C++ hotspot code in JDK-8261027 and optimized in JDK-8261649.
The acquire semantics in atomic instructions {ldaddal, swpal, casal} ensure that no subsequent accesses can pass the atomic operations.
While in current implementation, we also have a trailing dmb, it can ensure what the acquire does.
So the acquire semantics is no longer needed, {ldaddl, swpl, casl} would be enough.

Checked by using the herd7 consistency model simulator with similar test case in comments before `gen_cas_entry`:
AArch64 LseCas
{ 0:X1=x; 0:X2=y; 1:X1=x; 1:X2=y; }
P0 | P1;
LDR W4, [X2] | MOV W3, #0;
DMB LD | MOV W4, #1;
LDR W3, [X1] | CASL W3, W4, [X1];
                      | DMB ISH;
                      | STR W4, [X2];
exists
 (0:X3=0 /\ 0:X4=1)

No `X3 == 0 && X4 == 1` witnessed.

Similarly, the `ldaxr+stlxr+dmb` in default `atomic_fetch_add` and `atomic_xchg` can be replaced by `ldxr+stlxr+dmb`.