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Enhancement
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Resolution: Fixed
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P4
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17, 18
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b06
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x86
- Following instruction patterns emit extra redundant register to register moves.
MoveF2VL
MoveF2LEG
MoveVL2F
MoveLEG2F
MoveD2VL
MoveD2LEG
MoveVL2D
MoveLEG2D
- Register allocator is capable of constraining the register mask of DEF operand based on the register mask back propagated from USE operand.
MoveF2VL
MoveF2LEG
MoveVL2F
MoveLEG2F
MoveD2VL
MoveD2LEG
MoveVL2D
MoveLEG2D
- Register allocator is capable of constraining the register mask of DEF operand based on the register mask back propagated from USE operand.