Enhance macro logic optimization for masked logic operations.

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    • Type: Enhancement
    • Resolution: Fixed
    • Priority: P4
    • 19
    • Affects Version/s: 18
    • Component/s: hotspot
    • b05
    • x86_64
    • generic

      - Extend the existing algorithm to facilitate macro logic inferencing if constituents vector logic operations are predicated.
      - Support for masked Vector API BITWISE_BLEND operation.
      - X86 AVX512 targets have predicated VPTERNLOG instructions which can be emitted for evaluating masked logic expression tree.

            Assignee:
            Jatin Bhateja
            Reporter:
            Jatin Bhateja
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              Created:
              Updated:
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