- Extend the existing algorithm to facilitate macro logic inferencing if constituents vector logic operations are predicated.
- Support for masked Vector API BITWISE_BLEND operation.
- X86 AVX512 targets have predicated VPTERNLOG instructions which can be emitted for evaluating masked logic expression tree.
- Support for masked Vector API BITWISE_BLEND operation.
- X86 AVX512 targets have predicated VPTERNLOG instructions which can be emitted for evaluating masked logic expression tree.
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JDK-8294331 [TESTBUG] TestMaskedMacroLogicVector is part of tier3 on riscv
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- Resolved
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- Resolved
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JDK-8283103 compiler/vectorapi/TestMaskedMacroLogicVector.java failed due to incorrect os.simpleArch on some platforms
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- Open
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