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  1. JDK
  2. JDK-8278322

riscv: Support RVC: compressed instructions

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    • Icon: Enhancement Enhancement
    • Resolution: Withdrawn
    • Icon: P4 P4
    • repo-riscv-port
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      This patch support RISC-V RVC extension. It can introduce:
      * 21% code size reduction in template interpreter generated code
      * 20%~25% code size reduction in C1 generated code, evaluated by a common SpringBoot program
      * 15%~20% code size reduction in C2 generated code, evaluated by a common SpringBoot program

      In my observation, the code size footprint could be reduced to nearly a level of the AArch64 back-end. About the performance, there seems a stable ~0.7% performance improvement on SPECjbb2015 on one HiFive Unleashed board, considering the code density increase. I think the performance aspect might be a speculative behavior on different hardware implementations because C910's performance might be better than that, but HiFive Unleashed may be more general.

      Things about this patch:
      * If an instruction is compressible, then we will implicitly emit a 16-bit compressed instruction instead of the 32-bit instruction in Assembler.
      * About the `_nc` postfix of some of Assembler instructions: we know a bunch of places should be reserved for patching, where we cannot change them into compressed instructions. `_nc` is short for `not compressible` - with this, those instructions should keep their origin 4-byte form and remain uncompressed.
      * There are things not easy to compress like MachBranchNodes. Please see the comments in the code - currently this patch does not support this. We will support this improvement in patches coming afterward.

      The macros after their expansion might be like:
      ```
      void andr(Register Rd, Register Rs1, Register Rs2) {
      + {
      + Register src = noreg;
      + if (UseRVC && Rs1->is_compressed_valid() && Rs2->is_compressed_valid() &&
      + ((src = Rs1, Rs2 == Rd) || (src = Rs2, Rs1 == Rd))) {
      + and_c(Rd, src);
      + return;
      + }
      + }
        unsigned insn = 0;
        patch((address)&insn, 6, 0, 0b0110011);
        patch((address)&insn, 14, 12, 0b111);
        patch((address)&insn, 31, 25, 0b0000000);
        patch_reg((address)&insn, 7, Rd);
        patch_reg((address)&insn, 15, Rs1);
        patch_reg((address)&insn, 20, Rs2);
        emit(insn);
      };
      ```

      For further information, please see comments in `assembler_riscv_cext.hpp`.

            xlinzheng Xiaolin Zheng
            xlinzheng Xiaolin Zheng
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