The bit-manipulation (bitmanip) extension collection is comprised of several component extensions to the base RISC-V architecture that are intended to provide some combination of code size reduction, performance improvement, and energy reduction.

The RISC-V BitManipulation Extension (RVB) has released spec v1.0.0 for public review, which is stable enough to support in RISC-V backend.

The latest spec can be obtained from https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0.

This issue implements Add unsigned word instruction `add.uw` and sign- and zero-extension insturctions: `sext.b`, `sext.h` and `zext.h`