RISC-V Vector Extension adds 32 architectural vector registers to the base scalar RISC-V ISA, and does not overlay the f registers on v registers [1]. `is_wide_vector` should always return true when RVV is enabled.

On AArch64, the thirty two registers in the FP/SIMD register bank named V0 to V31 are used to hold floating point operands for the scalar floating point instructions, and both scalar and vector operands for the Advanced SIMD instructions [2]. 8 bytes vectors registers are saved by default on AArch64 [3].

[1]: https://github.com/riscv/riscv-v-spec
[2]: https://class.ece.uw.edu/469/peckol/doc/ARM/ARM_v8_Instruction_Set_Architecture_(Overview).pdf
[3]: https://github.com/openjdk/riscv-port/blob/4693b37234a03796b66073689ecf7d3548c99888/src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp#L275