AArch64: Add optimized rules for masked vector multiply-add/sub for SVE

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    • b17
    • aarch64

      We have the optimized match rules for vector "fmls,fnmla,fnmls,mla,mls" for ARM SVE. Similarly we can also add the rules for the relative masked operations to generate predicated instructions.

            Assignee:
            Xiaohong Gong
            Reporter:
            Xiaohong Gong
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