Currently, `elf_hwcap` for RISC-V only sets single-letter extension bit (e.g. IMAFD).
As many standard multi-letter ISA extensions are ratified (e.g. Zba/Zbb/Zbc/Zbs),
we should find a stable way to detect these supported ISA extensions in JVM.
[1] has proposed a way to parse supported extensions through /proc/cpuinfo
or "riscv,isa" string of /sys/firmware/devicetree, we could detect supported extensions
in the same way.

Here is an example of /proc/cpuinfo with multi-letter extensions from Ubuntu 20.04 in QEMU-SYSTEM:

```
ubuntu@ubuntu:~$ uname -a
Linux ubuntu 5.8.0-14-generic #16~20.04.3-Ubuntu SMP Mon Feb 1 16:33:19 UTC 2021 riscv64 riscv64 riscv64 GNU/Linux
ubuntu@ubuntu:~$ cat /proc/cpuinfo
processor : 0
hart : 2
isa : rv64imafdch_zicsr_zifencei_zihintpause_zba_zbb_zbc_zbs_sstc
mmu : sv48
```

[1]: http://lists.infradead.org/pipermail/linux-riscv/2021-November/010252.html