-
Bug
-
Resolution: Fixed
-
P5
-
19
Issue | Fix Version | Assignee | Priority | Status | Resolution | Resolved In Build |
---|---|---|---|---|---|---|
JDK-8311698 | 17.0.9 | Fei Yang | P5 | Resolved | Fixed | b01 |
On behalf of Dingli Zhang (dingli@iscas.ac.cn)
In `MacroAssembler::call_native_base`, t0 and xmethod should be saved as expected:
```
void MacroAssembler::call_native_base(address entry_point, Label *retaddr) {
Label E, L;
int32_t offset = 0;
push_reg(0x80000040, sp); // push << t0 & xmethod >> to sp
movptr_with_offset(t0, entry_point, offset);
jalr(x1, t0, offset);
if (retaddr != NULL) {
bind(*retaddr);
}
pop_reg(0x80000040, sp); // pop << t0 & xmethod >> from sp
}
```
Register mask of '0x80000040' operates << t1 & xmethod >> here, which should be '0x80000020' for << t0 & xmethod >>.
In `MacroAssembler::call_native_base`, t0 and xmethod should be saved as expected:
```
void MacroAssembler::call_native_base(address entry_point, Label *retaddr) {
Label E, L;
int32_t offset = 0;
push_reg(0x80000040, sp); // push << t0 & xmethod >> to sp
movptr_with_offset(t0, entry_point, offset);
jalr(x1, t0, offset);
if (retaddr != NULL) {
bind(*retaddr);
}
pop_reg(0x80000040, sp); // pop << t0 & xmethod >> from sp
}
```
Register mask of '0x80000040' operates << t1 & xmethod >> here, which should be '0x80000020' for << t0 & xmethod >>.
- backported by
-
JDK-8311698 riscv: Incorrect register mask in call_native_base
- Resolved
- links to
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Commit openjdk/jdk17u-dev/966fc82d
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Commit openjdk/jdk/b10833bb
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Commit openjdk/riscv-port-jdk11u/ec98a696
-
Review openjdk/jdk17u-dev/1427
-
Review openjdk/jdk/8353
-
Review openjdk/riscv-port-jdk11u/18
(2 links to)