AArch64: Fix register issues in SVE backend match rules

There are register issues in the sve backend match rules like "and_masked", "gatherL/scatterL".

The predicated vector "not" rules didn't use the same register for "src" and "dst", which is necessary to make sure the inactive lanes in "dst" save the same elements as "src". This could make the following results in array "ir" incorrect:
```
        VectorMask<Integer> mask = VectorMask.fromArray(I_SPECIES, m, 0);
        IntVector av = IntVector.fromArray(I_SPECIES, ia, 0);
        av.lanewise(VectorOperators.NOT, mask).add(av).intoArray(ir, 0);

```

And the input idx register in "gatherL/scatterL" rules was overwritten by the first unpack instruction. The same issue also existed in the partial and predicated gatherL/scatterL rules. The following case could reproduce this issue that the results in "ir" are incorrect:
```
        LongVector av = LongVector.fromArray(L_SPECIES, la, 0, ia, 0);
        av.intoArray(lr, 0);
        IntVector bv = IntVector.fromArray(I_SPECIES, ia, 0);
        bv.add(0).intoArray(ir, 0);
```