Details
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Enhancement
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Resolution: Fixed
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P4
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20
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b07
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riscv
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linux
Backports
Issue | Fix Version | Assignee | Priority | Status | Resolution | Resolved In Build |
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JDK-8311708 | 17.0.9 | Fei Yang | P4 | Resolved | Fixed | b01 |
Description
Currently, add_memory_int32/64 for riscv can only add a sign-extended 12-bit immediate to memory since they call addi/addiw assembler direcly.
This constraint could be relaxed when the given memory address is in the expected form: base register plus a sign-extended 12-bit offset. In this case, we can emit code for load + add/sub + store sequence adding arbitrary immediate to memory with no more than two scratch registers (t0 and t1) available.
We could also refactor these two functions into four seperate functions: increment, incrementw, decrement and decrementw, so that it will be more clear in code logic at the call sites.
This constraint could be relaxed when the given memory address is in the expected form: base register plus a sign-extended 12-bit offset. In this case, we can emit code for load + add/sub + store sequence adding arbitrary immediate to memory with no more than two scratch registers (t0 and t1) available.
We could also refactor these two functions into four seperate functions: increment, incrementw, decrement and decrementw, so that it will be more clear in code logic at the call sites.
Attachments
Issue Links
- backported by
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JDK-8311708 riscv: small refactoring for add_memory_int32/64
- Resolved
- links to
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Commit openjdk/jdk17u-dev/966fc82d
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Commit openjdk/jdk/92067e20
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Commit(riscv-port) openjdk/riscv-port-jdk11u/06f81133
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Review openjdk/jdk17u-dev/1427
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Review openjdk/jdk/9461
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Review openjdk/riscv-port-jdk17u/34
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Review(riscv-port) openjdk/riscv-port-jdk11u/30
(3 links to)