I have tried riscv builds of jdk on risc-v core ( running on fpga) without misaligned memory access support and without misaligned access emulation support in m-mode.
I have seen few errors ( SIG_ILL, ILL_ILLTRP), first one is in MacroAssembler::stop()

void MacroAssembler::stop(const char* msg) {
 BLOCK_COMMENT(msg);
 illegal_instruction(Assembler::csr::time);
 emit_int64((uintptr_t)msg);
}

the issue happens in inlined emit_int64. it's code:
 void emit_int64( int64_t x) { *((int64_t*) end()) = x; set_end(end() + sizeof(int64_t)); }

but the end() pointer is shared between multiple methods, like emit_int32, emit_int8, and non of them cares about natural type alignment, for example:
 void emit_int32(int32_t x) {
   address curr = end();
   *((int32_t*) curr) = x;
   set_end(curr + sizeof(int32_t));
 }

 void emit_int8(int8_t x1) {
   address curr = end();
   *((int8_t*) curr++) = x1;
   set_end(curr);
 }

I have worked around this issue by replacing one emit_int64 by two emit_int32 ( on lower and upper parts of msg ptr). It allowed me to pass this error, then next one appeared.
In templateInterpreter, in code generated for putStatic:
it has multiple entrance headers ( for stack setup) and one of them uses misaligned access ( lhu a3, 1(s6); it loads 16-bit value from address s6+1; where s6 is a pointer with even value).

0x3f89d033c0: ff8a0a13 addi s4,s4,-8
0x3f89d033c4: 00aa3023 sd a0,0(s4)
0x3f89d033c8: 0380006f j 56 # 0x3f89d03400
0x3f89d033cc: ff8a0a13 addi s4,s4,-8
0x3f89d033d0: 00aa2027 fsw fa0,0(s4)
0x3f89d033d4: 02c0006f j 44 # 0x3f89d03400
0x3f89d033d8: ff0a0a13 addi s4,s4,-16
0x3f89d033dc: 00aa3027 fsd fa0,0(s4)
0x3f89d033e0: 0200006f j 32 # 0x3f89d03400
0x3f89d033e4: ff0a0a13 addi s4,s4,-16
0x3f89d033e8: 000a3423 sd zero,8(s4)
0x3f89d033ec: 00aa3023 sd a0,0(s4)
0x3f89d033f0: 0100006f j 16 # 0x3f89d03400
0x3f89d033f4: ff8a0a13 addi s4,s4,-8
0x3f89d033f8: 0005053b addw a0,a0,zero
0x3f89d033fc: 00aa3023 sd a0,0(s4)
0x3f89d03400: 001b5683 lhu a3,1(s6). <— MISALLIGNED ACCESS
0x3f89d03404: 00569613 slli a2,a3,5
0x3f89d03408: 00cd0633 add a2,s10,a2
0x3f89d0340c: 02860493 addi s1,a2,40
0x3f89d03410: 00048493 mv s1,s1
0x3f89d03414: 0ff0000f fence iorw,iorw
0x3f89d03418: 0004e483 lwu s1,0(s1)
0x3f89d0341c: 0af0000f fence ir,iorw