Late barrier analysis for ZGC in C2 uses dominator information to elide load barriers. This information is computed at the beginning of the scheduler phase (PhaseCFG::build_dominator_tree()) and is invalidated whenever the block ordering phase (PhaseCFG::fixup_flow()) inserts a new block (PhaseCFG::insert_goto_at()). Invalid dominator information might lead to miscompilation of load barriers, even though no such event has been observed in practice.

The following example illustrates the issue. First, PhaseCFG::build_dominator_tree() computes the dominator tree (immediate dominators and depth) as part of scheduling (after-scheduling.pdf). After register allocation, PhaseCFG::fixup_flow() inserts a "goto" block between B3 and B5 (renamed to B4 and B7 in before-barrier-analysis.pdf). At this point, the dominator information is invalid (B5 lacks an immediate dominator, B7's immediate dominator should be B5, and B7's depth should be 5), and should be repaired or recomputed for a correct late barrier analysis.

Thanks to Nils Eliasson for discovering the issue and providing a tentative solution.