RISC-V: Add a second temporary register for BarrierSetAssembler::load_at

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    • Type: Enhancement
    • Resolution: Fixed
    • Priority: P4
    • 20
    • Affects Version/s: 20
    • Component/s: hotspot
    • None
    • gc
    • b16
    • riscv
    • linux

      This is similar to https://bugs.openjdk.org/browse/JDK-8293351

      Add a second temporary register for BarrierSetAssembler::load_at GC API on riscv64.

      Today G1 and Shenandoah uses a second temporary register. This will also be the case for generational ZGC.

            Assignee:
            Fei Yang
            Reporter:
            Fei Yang
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              Created:
              Updated:
              Resolved: