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Enhancement
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Resolution: Fixed
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P4
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20
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b23
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riscv
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linux
This patch will add support of `NegVI`, `NegVL` for RISC-V and was implemented by referring to aarch64 sve and RVV v1.0 [1].
After we implement this node, by using `-XX:+UseRVV`, the number of assembly instructions is reduced by about ~50% because of the different execution paths with the number of loops, similar to `AddTest` [2].
In the meantime, I also add an assembly pseudoinstruction `vneg.v` in macroAssembler_riscv.
[1] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#111-vector-single-width-integer-add-and-subtract
[2] https://github.com/zifeihan/vector-api-test-rvv/blob/master/vector-api-rvv-performance.md
After we implement this node, by using `-XX:+UseRVV`, the number of assembly instructions is reduced by about ~50% because of the different execution paths with the number of loops, similar to `AddTest` [2].
In the meantime, I also add an assembly pseudoinstruction `vneg.v` in macroAssembler_riscv.
[1] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#111-vector-single-width-integer-add-and-subtract
[2] https://github.com/zifeihan/vector-api-test-rvv/blob/master/vector-api-rvv-performance.md
