Backports
| Issue | Fix Version | Assignee | Priority | Status | Resolution | Resolved In Build |
|---|---|---|---|---|---|---|
| JDK-8311732 | 17.0.9 | Fei Yang | P4 | Resolved | Fixed | b01 |
Description
Some instructions previously had old assembler notation, but were renamed in RVV1.0[1][2] to be consistent with scalar instructions. We'd better keep the name the same as the new assembler mnemonics.
[1] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#152-vector-count-population-in-mask-vcpopm
[2] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#151-vector-mask-register-logical-instructions
[1] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#152-vector-count-population-in-mask-vcpopm
[2] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#151-vector-mask-register-logical-instructions
Attachments
Issue Links
- backported by
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JDK-8311732 RISC-V: Rename some assembler intrinsic functions for RVV 1.0
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- Resolved
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- links to
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Commit
openjdk/jdk17u-dev/966fc82d
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Commit
openjdk/jdk/2bd24c45
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Commit
openjdk/riscv-port-jdk17u/12e5b845
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Review
openjdk/jdk17u-dev/1427
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Review
openjdk/jdk/10878
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Review
openjdk/riscv-port-jdk17u/39
(2 links to)