P4 Description
Currently it's possible to completely disable SSE while keeping AVX enabled, e.g. -XX:UseSSE=0
This can cause some surprising asserts in tests when using some AVX instructions, and a need to sometimes guard features by the availability of both AVX at some level and SSE at some level,
Constraining AVX at any level require SSE to be fully enabled would help to reduce the number of hypothetical test targets. That is: disabling or limiting SSE should unconditionally disable AVX. Perhaps we need something slightly looser, though a cursory examination has not been able to find a CPU with AVX features that misses some or all SSE features.
This can cause some surprising asserts in tests when using some AVX instructions, and a need to sometimes guard features by the availability of both AVX at some level and SSE at some level,
Constraining AVX at any level require SSE to be fully enabled would help to reduce the number of hypothetical test targets. That is: disabling or limiting SSE should unconditionally disable AVX. Perhaps we need something slightly looser, though a cursory examination has not been able to find a CPU with AVX features that misses some or all SSE features.
