Details
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Enhancement
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Resolution: Fixed
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P4
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20
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b23
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riscv
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linux
Backports
| Issue | Fix Version | Assignee | Priority | Status | Resolution | Resolved In Build |
|---|---|---|---|---|---|---|
| JDK-8311734 | 17.0.9 | Fei Yang | P4 | Resolved | Fixed | b01 |
Description
At the moment, the operands order of `vrsub_vx` and ` vrsub_vi` is not the same as in the RVV1.0 spec[1]. These instructions use the wrong assembly syntax pattern for vector binary arithmetic instructions (multiply-add)[2].
[1] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc
[2] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#101-vector-arithmetic-instruction-encoding
[1] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc
[2] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#101-vector-arithmetic-instruction-encoding
Attachments
Issue Links
- backported by
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JDK-8311734 RISC-V: Make the operands order of vrsub_vx/vrsub_vi consistent with RVV 1.0 spec
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- Resolved
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- links to
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Commit
openjdk/jdk17u-dev/966fc82d
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Commit
openjdk/jdk/1169dc06
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Commit
openjdk/riscv-port-jdk17u/0884e87f
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Review
openjdk/jdk17u-dev/1427
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Review
openjdk/jdk/11009
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Review
openjdk/riscv-port-jdk17u/41
(2 links to)