RISC-V: Make the operands order of vrsub_vx/vrsub_vi consistent with RVV 1.0 spec

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    • Type: Enhancement
    • Resolution: Fixed
    • Priority: P4
    • 20
    • Affects Version/s: 20
    • Component/s: hotspot
    • b23
    • riscv
    • linux

        At the moment, the operands order of `vrsub_vx` and ` vrsub_vi` is not the same as in the RVV1.0 spec[1]. These instructions use the wrong assembly syntax pattern for vector binary arithmetic instructions (multiply-add)[2].

        [1] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc
        [2] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#101-vector-arithmetic-instruction-encoding

              Assignee:
              Dingli Zhang
              Reporter:
              Dingli Zhang
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                Created:
                Updated:
                Resolved: