-
Bug
-
Resolution: Fixed
-
P4
-
21
Issue | Fix Version | Assignee | Priority | Status | Resolution | Resolved In Build |
---|---|---|---|---|---|---|
JDK-8311748 | 17.0.9 | Fei Yang | P4 | Resolved | Fixed | b01 |
Witness that some c2 instructions use the inappropriate ins_pipe, e.g.:
```
instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
match(Set dst (MoveI2F src));
effect(DEF dst, USE src);
ins_cost(LOAD_COST);
format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}
ins_encode %{
__ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
%}
ins_pipe(pipe_class_memory);
%}
```
We can use the more accurate pipe_class `fp_load_mem_s` instead.
```
instruct MoveI2F_stack_reg(fRegF dst, stackSlotI src) %{
match(Set dst (MoveI2F src));
effect(DEF dst, USE src);
ins_cost(LOAD_COST);
format %{ "flw $dst, $src\t#@MoveI2F_stack_reg" %}
ins_encode %{
__ flw(as_FloatRegister($dst$$reg), Address(sp, $src$$disp));
%}
ins_pipe(pipe_class_memory);
%}
```
We can use the more accurate pipe_class `fp_load_mem_s` instead.
- backported by
-
JDK-8311748 RISC-V: pipeline class for several instructions is not set correctly
- Resolved
- links to
-
Commit openjdk/jdk17u-dev/966fc82d
-
Commit openjdk/jdk/9cc0171e
-
Commit openjdk/riscv-port-jdk17u/09020a43
-
Review openjdk/jdk17u-dev/1427
-
Review openjdk/jdk/12219
-
Review openjdk/riscv-port-jdk17u/61
(2 links to)