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  1. JDK
  2. JDK-8306667

RISC-V: Fix storeImmN0 matching rule by using zr register

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    • 19
    • b23
    • riscv
    • linux

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        The storeImmN0 matching rule as far as I know is from x86, which does not have a zero register. So it uses rheapbase as a zero register. The RISC-V backend ported this matching rule but did not specify the `CompressedOops::base() == NULL` predication so that under non-zero based compressed oops mode, the xheapbase can be a non-zero value and crashes the vm.

        Reproduced by `<JDK>/bin/java -Xcomp -XX:HeapBaseMinAddress=72030M -version` simply. An hs_err file is attached below, triggered by `-XX:HeapBaseMinAddress=72030M` by using a springboot-helloworld program.

        RISC-V also has a zero register x0, so we can use it to implement the matching rule.

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                xlinzheng Xiaolin Zheng
                xlinzheng Xiaolin Zheng
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                  Updated:
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