P4
A DESCRIPTION OF THE PROBLEM :
Currently, when a AND node is followed by a CMP node and the AND node operates on two registeres, a "and" and "test" instruction would be emitted. This can be optimized to use a single "test" instruction, the removed "and" means 2 bytes less have to be emitted. The Architecture Description file currently only handles the cases where the right operand of the And-Node is a constant, but not if both are a register.
I have already opened a PR for this issue: https://github.com/openjdk/jdk/pull/13587
Microbenchmarks result from that show an improvement from 0-29%.
Currently, when a AND node is followed by a CMP node and the AND node operates on two registeres, a "and" and "test" instruction would be emitted. This can be optimized to use a single "test" instruction, the removed "and" means 2 bytes less have to be emitted. The Architecture Description file currently only handles the cases where the right operand of the And-Node is a constant, but not if both are a register.
I have already opened a PR for this issue: https://github.com/openjdk/jdk/pull/13587
Microbenchmarks result from that show an improvement from 0-29%.
