AArch64: Vector registers are clobbered by some macroassemblers

The code below will generate different results with -XX:+UseSIMDForArrayEquals and -XX:-UseSIMDForArraysEquals. Root cause is, MacroAssembler::arrays_equals() will call to stub code which uses vector registers, but the match rule does not claim the use of vector registers.


import java.util.Arrays;
import java.util.Random;

public class RegStress {
    char [] ca;
    char [] cb;
    char [] cc;

    final int LENGTH = 1024;
    final int ITER = 20000;
    final int NUM = 20;
    float [] fv;
    
    int result = 0;

    public void init() {
        ca = new char[LENGTH];
        fv = new float[NUM];
        for (int i = 0; i < 20; i++) {
            fv[i] = i;
        }
        for (int i = 0; i < LENGTH; i++) {
            ca[i] = 0;
        }
        cb = ca.clone();
        cc = ca.clone();
    }

    public void checkArraysEquals() {
        float t1 = fv[0] + fv[1] + fv[2] + fv[3] + fv[4]
                   + fv[5] + fv[6] + fv[7] + fv[8] + fv[9]
                   + fv[10] + fv[11] + fv[12] + fv[13] + fv[14]
                   + fv[15] + fv[16] + fv[17] + fv[18] + fv[19];
        float t2 = 1.0f;
        if (Arrays.equals(ca, cb)) {
            t2 += fv[0] - fv[1] - fv[2] - fv[3] - fv[4]
                  + fv[5] - fv[6] - fv[7] - fv[8] - fv[9]
                  + fv[10] - fv[11] - fv[12] - fv[13] - fv[14]
                  + fv[15] - fv[16] - fv[17] - fv[18] - fv[19];
        }
        fv[19] = t1 + t2;
    }

    public void test() {
        for (int i = 0; i < ITER; i++) {
            checkArraysEquals();
        }
    }

    public void getResults() {
        System.out.println(fv[19]);
    }
    
    public static void main(String [] args) {
        RegStress t = new RegStress();
        t.init();
        t.test();
        t.getResults();
    }
}

Some other macroassemblers which have similar issue: encode_iso_array, string_indexof, arrays_equals, char_array_compress, byte_array_inflate, also need to be fixed.