Initial compiler support for FP16 scalar operations.

Starting with 4th Generation Xeon, Intel has made extensive extensions to existing ISA to support 16 bit scalar and vector floating point operations based on IEEE 754 FP16 format.

We plan to support this in multiple stages spanning across Java side definition of Float16 type, scalar operation and finally SLP vectorization support.

Following sub-tasks are needed for MVP support :-
- Minimal implementation of Float16 primitive class supporting one operation (Float16.add)
- X86 AVX512-FP16 feature detection at VM startup.
- C2 IR and Inline expander changes for Float16.add API.
- FP16 constant folding handling.
- Backend support : Instruction selection patterns and assembler support.