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  1. JDK
  2. JDK-8308915

RISC-V: Improve temporary vector register usage avoiding the use of v0

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    • Enhancement
    • Resolution: Fixed
    • P4
    • 21
    • 21
    • hotspot
    • b25
    • riscv
    • linux

    Description

      We have some macro assembler functions that use v0 hardcoded as a temporary register currently.
      However, the mask value used to control execution of a masked vector instruction is always supplied by vector register v0 in RVV1.0[1]. So if v0 is not used as a mask register in subsequent instructions, it is better to replace it with other vector registers to improve code execution efficiency.

      [1] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc

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              dzhang Dingli Zhang
              dzhang Dingli Zhang
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                Created:
                Updated:
                Resolved: