We have some macro assembler functions that use v0 hardcoded as a temporary register currently.
However, the mask value used to control execution of a masked vector instruction is always supplied by vector register v0 in RVV1.0[1]. So if v0 is not used as a mask register in subsequent instructions, it is better to replace it with other vector registers to improve code execution efficiency.

[1] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc