RISC-V: Make use of vl1r.v & vfabs.v pseudo-instructions where appropriate

We should add assembler functions for two pseudo-instructions vl1r.v [1] & vfabs.v [2] and use them when appropriate for better readability.

[1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#79-vector-loadstore-whole-register-instructions
[2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#1312-vector-floating-point-sign-injection-instructions