-
Enhancement
-
Resolution: Fixed
-
P4
-
22
-
b07
-
riscv
-
linux
Issue | Fix Version | Assignee | Priority | Status | Resolution | Resolved In Build |
---|---|---|---|---|---|---|
JDK-8312389 | 21.0.1 | Vladimir Kempik | P4 | Resolved | Fixed | b04 |
JDK-8312219 | 17.0.9 | Vladimir Kempik | P4 | Resolved | Fixed | b01 |
We sometimes emit this code in risc-v backend:
slli Rd, Rs, 0
(for example we do this in String.IndexOf intrinsic)
it's an equivalent of addi Rd, Rs, 0 ( a synonym for mv Rd, Rs)
addi with 0 has higher chances to be just a register renaming in decoder and not utilise ALU.
We observed some positive effect of replacing slli by 0 with addi on hifive.
slli Rd, Rs, 0
(for example we do this in String.IndexOf intrinsic)
it's an equivalent of addi Rd, Rs, 0 ( a synonym for mv Rd, Rs)
addi with 0 has higher chances to be just a register renaming in decoder and not utilise ALU.
We observed some positive effect of replacing slli by 0 with addi on hifive.
- backported by
-
JDK-8312219 RISC-V: small improvements to shift immediate instructions
- Resolved
-
JDK-8312389 RISC-V: small improvements to shift immediate instructions
- Resolved
- links to
-
Commit openjdk/jdk17u-dev/d79c2ef1
-
Commit openjdk/jdk21u/1776b3d2
-
Commit openjdk/jdk/f3b96f69
-
Review openjdk/jdk17u-dev/1584
-
Review openjdk/jdk21u/10
-
Review openjdk/jdk/14823
(3 links to)