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Enhancement
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Resolution: Fixed
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P4
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22
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b24
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riscv
Issue | Fix Version | Assignee | Priority | Status | Resolution | Resolved In Build |
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JDK-8323388 | 21.0.3-oracle | Fei Yang | P4 | Resolved | Fixed | b01 |
JDK-8320158 | 21.0.2 | Fei Yang | P4 | Resolved | Fixed | b08 |
JDK-8320226 | 17.0.10 | Gui Cao | P4 | Resolved | Fixed | b04 |
* do the buffer loads more incrementally instead of all in one go
* we don't have to mask off the top 32 bits of a register before an addw (and we don't need the mask32 register)
The changes show a 1.5%-2% improvement on a VisionFive 2 board.
- backported by
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JDK-8320158 RISC-V: improve MD5 intrinsic
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- Resolved
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JDK-8320226 RISC-V: improve MD5 intrinsic
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- Resolved
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JDK-8323388 RISC-V: improve MD5 intrinsic
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- Resolved
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- relates to
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JDK-8313322 RISC-V: implement MD5 intrinsic
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- Resolved
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- links to
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Commit openjdk/jdk17u-dev/49d5323e
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Commit openjdk/jdk21u/dfca3b95
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Commit openjdk/jdk/fa331d71
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Review openjdk/jdk17u-dev/1960
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Review openjdk/jdk21u/360
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Review openjdk/jdk/16453