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  1. JDK
  2. JDK-8331281

RISC-V: C2: Support vector-scalar and vector-immediate bitwise logic instructions

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    • b24
    • riscv
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      Hi, we want to support vector-scalar and vector-immediate bitwise logic instructions, It was implemented by referring to RVV v1.0 [1]. please take a look and have some reviews. Thanks a lot.
      We can use the Int256VectorTests.java[2] to print the compilation log, verify and observe the generation of nodes.

      For example, we can use the following command to print the compilation log of a jtreg test case:

      ```
      /home/zifeihan/jdk-tools/jtreg/bin/jtreg \
      -v:default \
      -concurrency:16 -timeout:50 \
      -javaoption:-XX:+UnlockExperimentalVMOptions \
      -javaoption:-XX:+UseRVV \
      -javaoption:-XX:+PrintOptoAssembly \
      -javaoption:-XX:LogFile=/home/zifeihan/jdk/Int256VectorTests_PrintOptoAssembly.log \
      -jdk:/home/zifeihan/jdk/build/linux-riscv64-server-fastdebug/jdk \
      /home/zifeihan/jdk/test/jdk/jdk/incubator/vector/Int256VectorTests.java
      ```


       we can observe the specified compilation log `Int256VectorTests_PrintOptoAssembly.log`, which contains the vector-scalar and vector-immediate bitwise logic node for the PR implementation.

      vand_immI Node

      ```
      0b4 vloadcon V3 # generate iota indices
      0bc vmla V2, V2, V3, V1
      0c4 vand_immI V2, V2, #7
      0cc addi R7, R30, #16 # ptr, #@addP_reg_imm
      0d0 storeV [R7], V2 # vector (rvv)
      ```

      vor_regI Node

      ```
      180 vor_regI V1, V1, R30
      188 add R31, R14, R31 # ptr, #@addP_reg_reg
      18a addi R31, R31, #16 # ptr, #@addP_reg_imm
      18c storeV [R31], V1 # vector (rvv)
      194 addiw R11, R11, #8 #@addI_reg_imm
      196 blt R11, R13, B17 #@cmpI_loop P=0.500000 C=30564.000000
      ```

      vxor_regI
      ```
      198 vxor_regI V1, V1, R30
      1a0 add R14, R16, R14 # ptr, #@addP_reg_reg
      1a2 addi R14, R14, #16 # ptr, #@addP_reg_imm
      1a4 storeV [R14], V1 # vector (rvv)
      1ac addiw R11, R11, #8 #@addI_reg_imm
      1ae blt R11, R13, B21 #@cmpI_loop P=0.500000 C=30564.000000
      ```

      vnotI Node

      ```
      13c B23: # out( B52 B24 ) <- in( B22 ) Freq: 75.1106
      13c loadV V2, [R16] # vector (rvv)
      144 vnotI V2, V2
      14c vand V1, V1, V2
      154 bgeu R9, R12, B52 #@cmpU_branch P=0.000001 C=-1.000000
      ```

      [1] https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc
      [2] https://github.com/openjdk/jdk/blob/master/test/jdk/jdk/incubator/vector/Int256VectorTests.java

            gcao Gui Cao
            gcao Gui Cao
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              Created:
              Updated:
              Resolved: